From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Arnd Bergmann <arnd@arndb.de>,
Andrew Murray <andrew.murray@arm.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>
Subject: Re: [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
Date: Thu, 19 Dec 2019 18:43:05 +0530 [thread overview]
Message-ID: <2c6984cc-731a-622f-7d90-c53e22f09f7b@ti.com> (raw)
In-Reply-To: <20191219000841.GA4251@bogus>
Hi,
On 19/12/19 5:38 am, Rob Herring wrote:
> On Mon, Dec 09, 2019 at 02:51:43PM +0530, Kishon Vijay Abraham I wrote:
>> Add host mode dt-bindings for TI's J721E SoC.
>>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> .../bindings/pci/ti,j721e-pci-host.yaml | 161 ++++++++++++++++++
>> 1 file changed, 161 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>> new file mode 100644
>> index 000000000000..96184e1f419f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>> @@ -0,0 +1,161 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: TI J721E PCI Host (PCIe Wrapper)
>> +
>> +maintainers:
>> + - Kishon Vijay Abraham I <kishon@ti.com>
>
> There's now a PCI bus schema. Reference it here:
>
> allOf:
> - $ref: "/schemas/pci/pci-bus.yaml#"
>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - ti,j721e-pcie-host
>
> Indentation.
>
>> +
>> + reg:
>> + maxItems: 4
>> +
>> + reg-names:
>> + items:
>> + - const: intd_cfg
>> + - const: user_cfg
>> + - const: reg
>> + - const: cfg
>> +
>> + ti,syscon-pcie-ctrl:
>> + description: Phandle to the SYSCON entry required for configuring PCIe mode
>> + and link speed.
>> + allOf:
>> + - $ref: /schemas/types.yaml#/definitions/phandle
>
> You can drop the 'allOf' here if there aren't more constraints.
>
>> +
>> + max-link-speed:
>> + minimum: 1
>> + maximum: 3
>> +
>> + num-lanes:
>> + minimum: 1
>> + maximum: 2
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> + description: clock-specifier to represent input to the PCIe
>> +
>> + clock-names:
>> + items:
>> + - const: fck
>> +
>
>> + "#address-cells":
>> + const: 3
>> +
>> + "#size-cells":
>> + const: 2
>> +
>> + bus-range:
>> + description: Range of bus numbers associated with this controller.
>
> Drop these 3 as they are all standard.
>
>> +
>> + cdns,max-outbound-regions:
>> + description: As defined in
>> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
>> + allOf:
>> + - $ref: /schemas/types.yaml#/definitions/int32
>
> Can be negative? Use uint32.
>
> The int* definitions are kind of broken until dtc is fixed to maintain
> sign.
>
>> + - enum: [16]
>
> const: 16
>
>> +
>> + cdns,no-bar-match-nbits:
>> + description: As defined in
>> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
>> + allOf:
>> + - $ref: /schemas/types.yaml#/definitions/int32
>> + - enum: [64]
>> +
>> + vendor-id:
>> + const: 0x104c
>> + description: As defined in
>> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
>
> And elsewhere. Drop the description.
>
>> +
>> + device-id:
>> + const: 0xb00d
>> + description: As defined in
>> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
>> +
>> + msi-map: true
>> +
>> + dma-coherent:
>> + description: Indicates that the PCIe IP block can ensure the coherency
>> +
>> + ranges: true
>
> Don't you know how many?
>
>> +
>> + reset-gpios:
>> + description: GPIO specifier for the PERST# signal
>> +
>> + phys:
>> + description: As defined in
>> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
>> +
>> + phy-names:
>> + description: As defined in
>> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - ti,syscon-pcie-ctrl
>> + - max-link-speed
>> + - num-lanes
>> + - power-domains
>> + - clocks
>> + - clock-names
>
>> + - "#address-cells"
>> + - "#size-cells"
>
> Can drop these 2. The bus schema requires them.
>
>> + - bus-range
>> + - cdns,max-outbound-regions
>> + - cdns,no-bar-match-nbits
>> + - vendor-id
>> + - device-id
>> + - msi-map
>> + - dma-coherent
>> + - ranges
>
> Can drop, too.
>
>> + - reset-gpios
>
> Isn't having this board dependent?
All board dts files should have it though.
I'll fix all the comments given here.
Thanks
Kishon
next prev parent reply other threads:[~2019-12-19 13:11 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 9:21 [PATCH 00/13] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
2019-12-16 13:45 ` Andrew Murray
2019-12-19 8:31 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 02/13] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-12-16 14:07 ` Andrew Murray
2019-12-19 11:41 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2019-12-17 11:58 ` Andrew Murray
2019-12-19 12:01 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-12-09 21:15 ` Bjorn Helgaas
2019-12-16 14:49 ` Andrew Murray
2019-12-19 11:56 ` Kishon Vijay Abraham I
2019-12-19 12:03 ` Arnd Bergmann
2019-12-19 13:19 ` Kishon Vijay Abraham I
2019-12-19 20:16 ` Arnd Bergmann
2019-12-17 23:36 ` Bjorn Helgaas
2019-12-19 12:49 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2019-12-17 12:32 ` Andrew Murray
2019-12-19 12:02 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2019-12-17 12:40 ` Andrew Murray
2019-12-19 12:03 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-12-17 12:42 ` Andrew Murray
2019-12-19 12:12 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2019-12-19 0:08 ` Rob Herring
2019-12-19 13:13 ` Kishon Vijay Abraham I [this message]
2019-12-24 8:06 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 10/13] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2019-12-19 0:14 ` Rob Herring
2019-12-19 13:14 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-12-17 14:23 ` Andrew Murray
2019-12-19 22:47 ` Bjorn Helgaas
2019-12-09 9:21 ` [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
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