From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Rob Herring <robh@kernel.org>
Cc: shruthi.sanil@intel.com, daniel.lezcano@linaro.org,
tglx@linutronix.de, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, kris.pan@linux.intel.com,
mgross@linux.intel.com, srikanth.thokala@intel.com,
lakshmi.bai.raja.subramanian@intel.com,
mallikarjunappa.sangannavar@intel.com
Subject: Re: [PATCH v4 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
Date: Wed, 14 Jul 2021 12:04:25 +0300 [thread overview]
Message-ID: <YO6ome7Opd6kjqua@smile.fi.intel.com> (raw)
In-Reply-To: <20210714024756.GA1355219@robh.at.kernel.org>
On Tue, Jul 13, 2021 at 08:47:56PM -0600, Rob Herring wrote:
> On Mon, Jun 28, 2021 at 11:44:09AM +0530, shruthi.sanil@intel.com wrote:
> > + The parent node represents the common general configuration details and
> > + the child nodes represents the counter and timers.
>
> I don't think all the child nodes are necessary. Are the counters and
> timers configurable (say on another SoC)? If not, then a single node
> here would suffice.
If you may notice the children may have different properties that can't be
known ahead, such as IRQ line. On some platforms it may be this mapping, on
another it maybe different.
With all respect for the simplification I think we can't do it here.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2021-07-14 9:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-28 6:14 [PATCH v4 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2021-06-28 6:14 ` [PATCH v4 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2021-07-14 2:47 ` Rob Herring
2021-07-14 9:04 ` Andy Shevchenko [this message]
2021-07-14 14:07 ` Rob Herring
2021-07-14 14:20 ` Andy Shevchenko
2021-07-15 8:01 ` Sanil, Shruthi
2021-07-22 9:57 ` Sanil, Shruthi
2021-06-28 6:14 ` [PATCH v4 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
2021-07-13 5:08 ` [PATCH v4 0/2] Add the driver for Intel Keem Bay SoC timer block Sanil, Shruthi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YO6ome7Opd6kjqua@smile.fi.intel.com \
--to=andriy.shevchenko@linux.intel.com \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=kris.pan@linux.intel.com \
--cc=lakshmi.bai.raja.subramanian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mallikarjunappa.sangannavar@intel.com \
--cc=mgross@linux.intel.com \
--cc=robh@kernel.org \
--cc=shruthi.sanil@intel.com \
--cc=srikanth.thokala@intel.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).