From: Sherry Sun <sherry.sun@nxp.com>
To: bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com,
james.morse@arm.com, rrichter@marvell.com,
michal.simek@xilinx.com, manish.narani@xilinx.com
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-imx@nxp.com, frank.li@nxp.com
Subject: [patch v3 1/4] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc
Date: Thu, 2 Apr 2020 09:20:30 +0800 [thread overview]
Message-ID: <1585790433-31465-2-git-send-email-sherry.sun@nxp.com> (raw)
In-Reply-To: <1585790433-31465-1-git-send-email-sherry.sun@nxp.com>
Add documentation for i.MX8MP DDRC binding based on synopsys_edac doc,
which use the same memory-controller IP.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index 9d32762c47e1..4fd14ba61474 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -6,16 +6,20 @@ bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
-These both ECC controllers correct single bit ECC errors and detect double bit
+The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width
+configurations.
+
+All the ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
Required properties:
- compatible: One of:
- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
+ - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller
- reg: Should contain DDR controller registers location and length.
-Required properties for "xlnx,zynqmp-ddrc-2.40a":
+Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc":
- interrupts: Property with a value describing the interrupt number.
Example:
--
2.17.1
next prev parent reply other threads:[~2020-04-02 1:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-02 1:20 [patch v3 0/4] Add edac driver for i.MX8MP based on synopsys edac driver Sherry Sun
2020-04-02 1:20 ` Sherry Sun [this message]
2020-04-02 1:20 ` [patch v3 2/4] EDAC: Add synopsys edac driver support for i.MX8MP Sherry Sun
2020-04-02 1:20 ` [patch v3 3/4] EDAC: synopsys: Add " Sherry Sun
2020-04-02 7:22 ` Robert Richter
2020-04-02 9:06 ` Sherry Sun
2020-04-02 11:17 ` Robert Richter
2020-04-02 13:09 ` Sherry Sun
2020-04-08 6:40 ` Robert Richter
2020-04-02 1:20 ` [patch v3 4/4] EDAC: synopsys: Add useful debug and output information for 64bit systems Sherry Sun
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1585790433-31465-2-git-send-email-sherry.sun@nxp.com \
--to=sherry.sun@nxp.com \
--cc=bp@alien8.de \
--cc=frank.li@nxp.com \
--cc=james.morse@arm.com \
--cc=linux-edac@vger.kernel.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=manish.narani@xilinx.com \
--cc=mchehab@kernel.org \
--cc=michal.simek@xilinx.com \
--cc=rrichter@marvell.com \
--cc=tony.luck@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).