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Wed, 21 Aug 2019 23:59:58 +0000 From: "Ghannam, Yazen" To: "linux-edac@vger.kernel.org" CC: "Ghannam, Yazen" , "linux-kernel@vger.kernel.org" , "bp@alien8.de" Subject: [PATCH v3 3/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels Thread-Topic: [PATCH v3 3/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels Thread-Index: AQHVWHyIDoXglb097EC3hpkcG3/nbg== Date: Wed, 21 Aug 2019 23:59:57 +0000 Message-ID: <20190821235938.118710-4-Yazen.Ghannam@amd.com> References: <20190821235938.118710-1-Yazen.Ghannam@amd.com> In-Reply-To: <20190821235938.118710-1-Yazen.Ghannam@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN2PR01CA0006.prod.exchangelabs.com (2603:10b6:804:2::16) To SN6PR12MB2639.namprd12.prod.outlook.com (2603:10b6:805:6f::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c65b91f9-88eb-4a8b-b617-08d72693ab0e x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2815; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c65b91f9-88eb-4a8b-b617-08d72693ab0e X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Aug 2019 23:59:57.2538 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xcBNBQcRnNCL9fhVnWb7gs2zN6PanguhRrHVr5acN3kuzaq6UpkH4yq7CoKgckgC+lNpliFYegIiY2De69Et1A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2815 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Yazen Ghannam Currently, the DIMM info for AMD Family 17h systems is initialized in init_csrows(). This function is shared with legacy systems, and it has a limit of two channel support. This prevents initialization of the DIMM info for a number of ranks, so there will be missing ranks in the EDAC sysfs. Create a new init_csrows_df() for Family17h+ and revert init_csrows() back to pre-Family17h support. Loop over all channels in the new function in order to support systems with more than two channels. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20190709215643.171078-4-Yazen.Ghannam@amd.com v2->v3: * Drop Fixes: tag. * Add x8 DRAM device case. v1->v2: * No change. drivers/edac/amd64_edac.c | 66 ++++++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 14 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0e8b2137edbb..001dc85122e9 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2837,6 +2837,49 @@ static u32 get_csrow_nr_pages(struct amd64_pvt *pvt,= u8 dct, int csrow_nr_orig) return nr_pages; } =20 +static int init_csrows_df(struct mem_ctl_info *mci) +{ + struct amd64_pvt *pvt =3D mci->pvt_info; + enum edac_type edac_mode =3D EDAC_NONE; + enum dev_type dev_type =3D DEV_UNKNOWN; + struct dimm_info *dimm; + int empty =3D 1; + u8 umc, cs; + + if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) { + edac_mode =3D EDAC_S16ECD16ED; + dev_type =3D DEV_X16; + } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) { + edac_mode =3D EDAC_S8ECD8ED; + dev_type =3D DEV_X8; + } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) { + edac_mode =3D EDAC_S4ECD4ED; + dev_type =3D DEV_X4; + } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) { + edac_mode =3D EDAC_SECDED; + } + + for_each_umc(umc) { + for_each_chip_select(cs, umc, pvt) { + if (!csrow_enabled(cs, umc, pvt)) + continue; + + empty =3D 0; + dimm =3D mci->csrows[cs]->channels[umc]->dimm; + + edac_dbg(1, "MC node: %d, csrow: %d\n", + pvt->mc_node_id, cs); + + dimm->nr_pages =3D get_csrow_nr_pages(pvt, umc, cs); + dimm->mtype =3D pvt->dram_type; + dimm->edac_mode =3D edac_mode; + dimm->dtype =3D dev_type; + } + } + + return empty; +} + /* * Initialize the array of csrow attribute instances, based on the values * from pci config hardware registers. @@ -2851,15 +2894,16 @@ static int init_csrows(struct mem_ctl_info *mci) int nr_pages =3D 0; u32 val; =20 - if (!pvt->umc) { - amd64_read_pci_cfg(pvt->F3, NBCFG, &val); + if (pvt->umc) + return init_csrows_df(mci); + + amd64_read_pci_cfg(pvt->F3, NBCFG, &val); =20 - pvt->nbcfg =3D val; + pvt->nbcfg =3D val; =20 - edac_dbg(0, "node %d, NBCFG=3D0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n= ", - pvt->mc_node_id, val, - !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); - } + edac_dbg(0, "node %d, NBCFG=3D0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n"= , + pvt->mc_node_id, val, + !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); =20 /* * We iterate over DCT0 here but we look at DCT1 in parallel, if needed. @@ -2896,13 +2940,7 @@ static int init_csrows(struct mem_ctl_info *mci) edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages); =20 /* Determine DIMM ECC mode: */ - if (pvt->umc) { - if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) - edac_mode =3D EDAC_S4ECD4ED; - else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) - edac_mode =3D EDAC_SECDED; - - } else if (pvt->nbcfg & NBCFG_ECC_ENABLE) { + if (pvt->nbcfg & NBCFG_ECC_ENABLE) { edac_mode =3D (pvt->nbcfg & NBCFG_CHIPKILL) ? EDAC_S4ECD4ED : EDAC_SECDED; --=20 2.17.1