From: Tony Luck <tony.luck@intel.com>
To: linux-edac@vger.kernel.org
Cc: Tony Luck <tony.luck@intel.com>, Borislav Petkov <bp@alien8.de>,
Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
Aristeu Rozanski <aris@redhat.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: [PATCH 0/3] EDAC - fix for i10nm driver + upgrade to support Sapphire Rapids
Date: Thu, 19 Nov 2020 13:22:16 -0800 [thread overview]
Message-ID: <20201119212219.1335-1-tony.luck@intel.com> (raw)
First patch is a bug fix (sort of) we haven't directly seen problems
in the driver, but when adding other bits to it there have been cases
where the compiler re-ordered the access to the MMIO registers. Which
can be a problem.
Second patch adds new type for DDR5 memory
Final patch updates the i10nm EDAC driver to support Sapphire Rapids.
This series on top of:
git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-igen6
(which also adds some new memory types)
Qiuxu Zhuo (3):
EDAC/i10nm: Use readl() to access MMIO registers
EDAC: Add DDR5 new memory type
EDAC/i10nm: Add Intel Sapphire Rapids server support
drivers/edac/edac_mc.c | 1 +
drivers/edac/i10nm_base.c | 39 +++++++++++++++++++++++++++++----------
drivers/edac/skx_base.c | 6 +++---
drivers/edac/skx_common.c | 23 ++++++++++++++++++-----
drivers/edac/skx_common.h | 16 ++++++++++++----
include/linux/edac.h | 3 +++
6 files changed, 66 insertions(+), 22 deletions(-)
--
2.21.1
next reply other threads:[~2020-11-19 21:22 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 21:22 Tony Luck [this message]
2020-11-19 21:22 ` [PATCH 1/3] EDAC/i10nm: Use readl() to access MMIO registers Tony Luck
2020-11-19 21:22 ` [PATCH 2/3] EDAC: Add DDR5 new memory type Tony Luck
2020-11-19 21:22 ` [PATCH 3/3] EDAC/i10nm: Add Intel Sapphire Rapids server support Tony Luck
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