From: Sascha Hauer <s.hauer@pengutronix.de>
To: Mark Rutland <mark.rutland@arm.com>
Cc: linux-edac@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
Rob Herring <robh+dt@kernel.org>,
Robert Richter <rrichter@marvell.com>,
James Morse <james.morse@arm.com>,
kernel@pengutronix.de, Borislav Petkov <bp@alien8.de>,
York Sun <york.sun@nxp.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/1] drivers/edac: Add L1 and L2 error detection for A53 and A57
Date: Thu, 7 Jan 2021 13:36:32 +0100 [thread overview]
Message-ID: <20210107123632.GX19063@pengutronix.de> (raw)
In-Reply-To: <20210107111520.GA7523@C02TD0UTHF1T.local>
On Thu, Jan 07, 2021 at 11:15:20AM +0000, Mark Rutland wrote:
> Hi Sascha,
>
> On Thu, Jan 07, 2021 at 11:38:19AM +0100, Sascha Hauer wrote:
> > The Cortex A53 and A57 cores have error detection capabilities for the
> > L1/L2 Caches, this patch adds a driver for them.
> >
> > Unfortunately there is no robust way to inject errors into the caches,
> > so this driver doesn't contain any code to actually test it. It has
> > been tested though with code taken from an older version of this driver
> > found here: https://lkml.org/lkml/2018/3/14/1203. For reasons stated
> > in this thread the error injection code is not suitable for mainline,
> > so it is removed from the driver.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > drivers/edac/Kconfig | 6 +
> > drivers/edac/Makefile | 1 +
> > drivers/edac/cortex_arm64_l1_l2.c | 218 ++++++++++++++++++++++++++++++
> > 3 files changed, 225 insertions(+)
> > create mode 100644 drivers/edac/cortex_arm64_l1_l2.c
>
> [...]
>
> > +#define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2)
> > +#define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3)
>
> Just to note -- these registers are IMPLEMENTATION DEFINED, and so may
> be trapped by a hypervisor or messed around with arbitrarily by FW.
>
> > +static void read_errors(void *data)
> > +{
> > + struct merrsr *merrsr = data;
> > +
> > + merrsr->cpumerr = read_sysreg_s(SYS_CPUMERRSR_EL1);
> > + write_sysreg_s(0, SYS_CPUMERRSR_EL1);
> > + merrsr->l2merr = read_sysreg_s(SYS_L2MERRSR_EL1);
> > + write_sysreg_s(0, SYS_L2MERRSR_EL1);
> > +}
>
> ... and so here the MRS instructions may behave as UNDEFINED in some
> cases. Foer example, KVM would trap these via HCR_EL2.TIDCP, and emulate
> these as UNDEFINED.
>
> > +static const struct of_device_id cortex_arm64_edac_of_match[] = {
> > + { .compatible = "arm,cortex-a53" },
> > + { .compatible = "arm,cortex-a57" },
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, cortex_arm64_edac_of_match);
>
> ... and so it's not safe to probe this based on the CPU compatible
> string alone. If we really need to support this, it will need its own
> binding (to describe that the reigsters are safe to access and behave in
> a useful way).
Rob objected to adding dedicated nodes to attach the driver to. That
leaves adding a property like "edac-enabled" or similar to the CPU nodes
when edac is desired. Would that be ok?
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
prev parent reply other threads:[~2021-01-07 12:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 10:38 [PATCH v3 0/1] Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2021-01-07 10:38 ` [PATCH 1/1] drivers/edac: " Sascha Hauer
2021-01-07 11:05 ` Marc Zyngier
2021-01-07 11:15 ` Mark Rutland
2021-01-07 12:36 ` Sascha Hauer [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210107123632.GX19063@pengutronix.de \
--to=s.hauer@pengutronix.de \
--cc=bp@alien8.de \
--cc=james.morse@arm.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-edac@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mchehab@kernel.org \
--cc=robh+dt@kernel.org \
--cc=rrichter@marvell.com \
--cc=tony.luck@intel.com \
--cc=york.sun@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).