From: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
To: x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Tony Luck <tony.luck@intel.com>,
"H . Peter Anvin" <hpa@zytor.com>,
yazen.ghannam@amd.com, Smita.KoralahalliChannabasappa@amd.com
Subject: [PATCH 3/5] x86/mce: Use msr_ops in prepare_msrs()
Date: Wed, 15 Sep 2021 18:27:37 -0500 [thread overview]
Message-ID: <20210915232739.6367-4-Smita.KoralahalliChannabasappa@amd.com> (raw)
In-Reply-To: <20210915232739.6367-1-Smita.KoralahalliChannabasappa@amd.com>
Replace MCx_{STATUS, ADDR, MISC} macros with msr_ops.
Also, restructure the code to avoid multiple initializations for MCA
registers. SMCA machines define a different set of MSRs for MCA registers
and msr_ops initializes appropriate MSRs for SMCA and legacy processors.
Initialize MCA_MISC and MCA_SYND registers at the end after initializing
MCx_{STATUS, DESTAT} which is further explained in the next patch.
Make msr_ops exportable in order to be accessible from mce-inject module.
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
---
arch/x86/kernel/cpu/mce/core.c | 1 +
arch/x86/kernel/cpu/mce/inject.c | 27 +++++++++++++--------------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 193204aee880..9af910acb930 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -222,6 +222,7 @@ struct mca_msr_regs msr_ops = {
.addr = addr_reg,
.misc = misc_reg
};
+EXPORT_SYMBOL_GPL(msr_ops);
static void __print_mce(struct mce *m)
{
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 8de709b049fc..8af4c9845f96 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -464,22 +464,21 @@ static void prepare_msrs(void *info)
wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
- if (boot_cpu_has(X86_FEATURE_SMCA)) {
- if (m.inject_flags == DFR_INT_INJ) {
- wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status);
- wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr);
- } else {
- wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status);
- wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr);
- }
+ if (boot_cpu_has(X86_FEATURE_SMCA) &&
+ m.inject_flags == DFR_INT_INJ) {
+ wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status);
+ wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr);
+ goto out;
+ }
+
+ wrmsrl(msr_ops.status(b), m.status);
+ wrmsrl(msr_ops.addr(b), m.addr);
- wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
+out:
+ wrmsrl(msr_ops.misc(b), m.misc);
+
+ if (boot_cpu_has(X86_FEATURE_SMCA))
wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);
- } else {
- wrmsrl(MSR_IA32_MCx_STATUS(b), m.status);
- wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr);
- wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
- }
}
static void do_inject(void)
--
2.17.1
next prev parent reply other threads:[~2021-09-15 23:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 23:27 [PATCH 0/5] x86/mce: Handle error simulation failures in mce-inject module Smita Koralahalli
2021-09-15 23:27 ` [PATCH 1/5] x86/mce/inject: Check if a bank is unpopulated before error simulation Smita Koralahalli
2021-09-24 8:26 ` Borislav Petkov
2021-09-27 19:51 ` Smita Koralahalli Channabasappa
2021-09-27 20:15 ` Borislav Petkov
2021-09-27 21:56 ` Smita Koralahalli Channabasappa
2021-09-27 22:05 ` Borislav Petkov
2021-10-11 21:12 ` Koralahalli Channabasappa, Smita
2021-10-14 18:22 ` Borislav Petkov
2021-10-14 20:26 ` Koralahalli Channabasappa, Smita
2021-10-14 20:57 ` Borislav Petkov
2021-09-15 23:27 ` [PATCH 2/5] x86/mce/inject: Set the valid bit in MCA_STATUS before error injection Smita Koralahalli
2021-09-24 8:26 ` Borislav Petkov
2021-09-15 23:27 ` Smita Koralahalli [this message]
2021-09-24 8:26 ` [PATCH 3/5] x86/mce: Use msr_ops in prepare_msrs() Borislav Petkov
2021-09-15 23:27 ` [PATCH 4/5] x86/mce/inject: Check for writes ignored in status registers Smita Koralahalli
2021-09-15 23:27 ` [PATCH 5/5] x86/mce/mce-inject: Return error code to userspace from mce-inject module Smita Koralahalli
2021-09-24 8:26 ` Borislav Petkov
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