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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
	tony.luck@intel.com
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, james.morse@arm.com,
	mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org,
	quic_ppareek@quicinc.com, luca.weiss@fairphone.com,
	ahalaney@redhat.com, steev@kali.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v8 13/14] qcom: llcc/edac: Support polling mode for ECC handling
Date: Tue, 14 Mar 2023 13:34:42 +0530	[thread overview]
Message-ID: <20230314080443.64635-14-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org>

Not all Qcom platforms support IRQ mode for ECC handling. For those
platforms, the current EDAC driver will not be probed due to missing ECC
IRQ in devicetree.

So add support for polling mode so that the EDAC driver can be used on all
Qcom platforms supporting LLCC.

The polling delay of 5000ms is chosen based on Qcom downstream/vendor
driver.

Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/edac/qcom_edac.c     | 50 +++++++++++++++++++++---------------
 drivers/soc/qcom/llcc-qcom.c | 13 +++++-----
 2 files changed, 35 insertions(+), 28 deletions(-)

diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
index 1d3cc1930a74..265e0fb39bc7 100644
--- a/drivers/edac/qcom_edac.c
+++ b/drivers/edac/qcom_edac.c
@@ -76,6 +76,8 @@
 #define DRP0_INTERRUPT_ENABLE           BIT(6)
 #define SB_DB_DRP_INTERRUPT_ENABLE      0x3
 
+#define ECC_POLL_MSEC			5000
+
 enum {
 	LLCC_DRAM_CE = 0,
 	LLCC_DRAM_UE,
@@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
 	return ret;
 }
 
-static irqreturn_t
-llcc_ecc_irq_handler(int irq, void *edev_ctl)
+static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl)
 {
 	struct edac_device_ctl_info *edac_dev_ctl = edev_ctl;
 	struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data;
@@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl)
 	return irq_rc;
 }
 
+static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl)
+{
+	llcc_ecc_irq_handler(0, edev_ctl);
+}
+
 static int qcom_llcc_edac_probe(struct platform_device *pdev)
 {
 	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
@@ -355,29 +361,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev)
 	edev_ctl->ctl_name = "llcc";
 	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
 
-	rc = edac_device_add_device(edev_ctl);
-	if (rc)
-		goto out_mem;
-
-	platform_set_drvdata(pdev, edev_ctl);
-
-	/* Request for ecc irq */
+	/* Check if LLCC driver has passed ECC IRQ */
 	ecc_irq = llcc_driv_data->ecc_irq;
-	if (ecc_irq < 0) {
-		rc = -ENODEV;
-		goto out_dev;
-	}
-	rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
+	if (ecc_irq > 0) {
+		/* Use interrupt mode if IRQ is available */
+		rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
 			      IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
-	if (rc)
-		goto out_dev;
+		if (!rc) {
+			edac_op_state = EDAC_OPSTATE_INT;
+			goto irq_done;
+		}
+	}
 
-	return rc;
+	/* Fall back to polling mode otherwise */
+	edev_ctl->poll_msec = ECC_POLL_MSEC;
+	edev_ctl->edac_check = llcc_ecc_check;
+	edac_op_state = EDAC_OPSTATE_POLL;
 
-out_dev:
-	edac_device_del_device(edev_ctl->dev);
-out_mem:
-	edac_device_free_ctl_info(edev_ctl);
+irq_done:
+	rc = edac_device_add_device(edev_ctl);
+	if (rc) {
+		edac_device_free_ctl_info(edev_ctl);
+		return rc;
+	}
+
+	platform_set_drvdata(pdev, edev_ctl);
 
 	return rc;
 }
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 72f3f2a9aaa0..7b7c5a38bac6 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 		goto err;
 
 	drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
-	if (drv_data->ecc_irq >= 0) {
-		llcc_edac = platform_device_register_data(&pdev->dev,
-						"qcom_llcc_edac", -1, drv_data,
-						sizeof(*drv_data));
-		if (IS_ERR(llcc_edac))
-			dev_err(dev, "Failed to register llcc edac driver\n");
-	}
+
+	llcc_edac = platform_device_register_data(&pdev->dev,
+					"qcom_llcc_edac", -1, drv_data,
+					sizeof(*drv_data));
+	if (IS_ERR(llcc_edac))
+		dev_err(dev, "Failed to register llcc edac driver\n");
 
 	return 0;
 err:
-- 
2.25.1


  parent reply	other threads:[~2023-03-14  8:07 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-14  8:04 [PATCH v8 00/14] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 01/14] dt-bindings: arm: msm: Update the maintainers for LLCC Manivannan Sadhasivam
2023-03-19 12:46   ` Krzysztof Kozlowski
2023-03-14  8:04 ` [PATCH v8 02/14] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 03/14] arm64: dts: qcom: sdm845: Fix the base addresses of " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 04/14] arm64: dts: qcom: sc7180: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 05/14] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 06/14] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 07/14] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 08/14] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 09/14] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 10/14] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 11/14] arm64: dts: qcom: sm6350: " Manivannan Sadhasivam
2023-03-14  8:04 ` [PATCH v8 12/14] qcom: llcc/edac: Fix the base address used for accessing " Manivannan Sadhasivam
2023-03-14  8:04 ` Manivannan Sadhasivam [this message]
2023-03-14  8:04 ` [PATCH v8 14/14] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Manivannan Sadhasivam
2023-03-15 23:35 ` (subset) [PATCH v8 00/14] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Bjorn Andersson

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