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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099D7.mail.protection.outlook.com (10.167.17.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7452.22 via Frontend Transport; Thu, 4 Apr 2024 15:14:21 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 4 Apr 2024 10:14:10 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 03/16] x86/mce/amd: Use fixed bank number for quirks Date: Thu, 4 Apr 2024 10:13:46 -0500 Message-ID: <20240404151359.47970-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240404151359.47970-1-yazen.ghannam@amd.com> References: <20240404151359.47970-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|PH7PR12MB5781:EE_ X-MS-Office365-Filtering-Correlation-Id: 32bc4052-ec9c-48c7-310a-08dc54b9e7b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Therefore, quirk conditions don't need to follow micro-architectural requirements. Currently, there is a quirk to filter some errors from the Instruction Fetch (IF) unit on specific models. The IF unit is represented by MCA bank 1 for these models. Related to this quirk is code to disable MCA Thresholding for the IF bank. Check the bank number for the quirks instead of determining the bank type. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lkml.kernel.org/r/20231118193248.1296798-8-yazen.ghannam@amd.com v1->v2: * No change. arch/x86/kernel/cpu/mce/amd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9a0133ef7e20..bc78e751dfcc 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -605,13 +605,12 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, bool amd_filter_mce(struct mce *m) { - enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); struct cpuinfo_x86 *c = &boot_cpu_data; /* See Family 17h Models 10h-2Fh Erratum #1114. */ if (c->x86 == 0x17 && c->x86_model >= 0x10 && c->x86_model <= 0x2F && - bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) + m->bank == 1 && XEC(m->status, 0x3f) == 10) return true; /* NB GART TLB error reporting is disabled by default. */ @@ -643,7 +642,7 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) } else if (c->x86 == 0x17 && (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { - if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) + if (bank != 1) return; msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); -- 2.34.1