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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099D6.mail.protection.outlook.com (10.167.17.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7452.22 via Frontend Transport; Thu, 4 Apr 2024 15:14:23 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 4 Apr 2024 10:14:12 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 07/16] x86/mce/amd: Simplify DFR handler setup Date: Thu, 4 Apr 2024 10:13:50 -0500 Message-ID: <20240404151359.47970-8-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240404151359.47970-1-yazen.ghannam@amd.com> References: <20240404151359.47970-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D6:EE_|PH7PR12MB6467:EE_ X-MS-Office365-Filtering-Correlation-Id: 82744762-fc75-4a85-9217-08dc54b9e978 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The LVT offset is 0x2 by convention, i.e. this is the default as listed in hardware documentation. However, the MCA registers may list a different LVT offset for this interrupt. The kernel should honor the value from the hardware. Simplify the enable flow by using the hardware-provided value. Any conflicts will be caught by setup_APIC_eilvt(). Conflicts on production systems can be handled as quirks, if needed. Also, rename the function using a "verb-first" style. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lkml.kernel.org/r/20231118193248.1296798-12-yazen.ghannam@amd.com v1->v2: * No change. arch/x86/kernel/cpu/mce/amd.c | 33 ++++++++++----------------------- 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index e8e78d91082b..32628a30a5c1 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -48,7 +48,6 @@ #define MSR_CU_DEF_ERR 0xC0000410 #define MASK_DEF_LVTOFF 0x000000F0 #define MASK_DEF_INT_TYPE 0x00000006 -#define DEF_LVT_OFF 0x2 #define DEF_INT_TYPE_APIC 0x2 #define INTR_TYPE_APIC 0x1 @@ -575,19 +574,9 @@ static int setup_APIC_mce_threshold(int reserved, int new) return reserved; } -static int setup_APIC_deferred_error(int reserved, int new) +static void enable_deferred_error_interrupt(void) { - if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, - APIC_EILVT_MSG_FIX, 0)) - return new; - - return reserved; -} - -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) -{ - u32 low = 0, high = 0; - int def_offset = -1, def_new; + u32 low = 0, high = 0, def_new; if (!mce_flags.succor) return; @@ -595,17 +584,15 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) return; + /* + * Trust the value from hardware. + * If there's a conflict, then setup_APIC_eilvt() will throw an error. + */ def_new = (low & MASK_DEF_LVTOFF) >> 4; - if (!(low & MASK_DEF_LVTOFF)) { - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); - def_new = DEF_LVT_OFF; - low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); - } + if (setup_APIC_eilvt(def_new, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) + return; - def_offset = setup_APIC_deferred_error(def_offset, def_new); - if ((def_offset == def_new) && - (deferred_error_int_vector != amd_deferred_error_interrupt)) - deferred_error_int_vector = amd_deferred_error_interrupt; + deferred_error_int_vector = amd_deferred_error_interrupt; if (!mce_flags.smca) low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; @@ -771,7 +758,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; - deferred_error_interrupt_enable(c); + enable_deferred_error_interrupt(); for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) -- 2.34.1