From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F748C43331 for ; Fri, 6 Sep 2019 16:29:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E9539206CD for ; Fri, 6 Sep 2019 16:29:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389270AbfIFQ3F (ORCPT ); Fri, 6 Sep 2019 12:29:05 -0400 Received: from foss.arm.com ([217.140.110.172]:59034 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389180AbfIFQ3F (ORCPT ); Fri, 6 Sep 2019 12:29:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA2701570; Fri, 6 Sep 2019 09:29:04 -0700 (PDT) Received: from [10.1.196.105] (unknown [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B94C3F59C; Fri, 6 Sep 2019 09:29:01 -0700 (PDT) Subject: Re: [PATCH v5 1/4] dt-bindings: EDAC: Add Amazon's Annapurna Labs L1 EDAC To: Rob Herring Cc: "Hawa, Hanna" , Mark Rutland , Borislav Petkov , Mauro Carvalho Chehab , David Miller , Greg Kroah-Hartman , Linus Walleij , Jonathan Cameron , Nicolas Ferre , "Paul E. McKenney" , "Woodhouse, David" , benh@amazon.com, "Krupnik, Ronen" , Talel Shenhar , Jonathan Chocron , "Hanoch, Uri" , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , linux-edac References: <20190805143911.12185-1-hhhawa@amazon.com> <20190805143911.12185-2-hhhawa@amazon.com> <20190821191704.GA32425@bogus> <1d23d7c5-cd7b-1512-5300-d43e82ba6dc1@amazon.com> From: James Morse Message-ID: <21050550-7629-e8f7-2d30-16c1858cf3cc@arm.com> Date: Fri, 6 Sep 2019 17:28:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Hi Rob, On 30/08/2019 22:50, Rob Herring wrote: > So KVM provides a semi-CortexA57? Code that runs on real h/w won't as a guest. KVM provides the architectural bits of Cortex-A57's EL1, when running on A57. Code that depends on EL2, won't run as a guest. Code that depends on some non-architectural behaviour of A57 won't work in a guest, (e.g. the PMU) Features the hypervisor doesn't completely support may get hidden. The aim is to provide an virtual CPU, it might not be exactly the same as the one you're running on. Hypervisors have to disable access to the imp-def registers as they may allow the guest to break its confinement. (e.g. messing with the L2 timing) Code using imp-def instructions at EL1 needs to know they aren't trapped/disabled by a higher exception level. If someone wants to emulate these, something would need a model of what those imp-def instructions do. Thanks, James