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From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for chip selects handling
Date: Mon, 19 Aug 2019 19:55:50 +0000	[thread overview]
Message-ID: <SN6PR12MB2639A73ABD69C62132FD0A2CF8A80@SN6PR12MB2639.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20190802064953.GA30661@zn.tnic>

> -----Original Message-----
> From: Borislav Petkov <bp@alien8.de>
> Sent: Friday, August 2, 2019 1:50 AM
> To: Ghannam, Yazen <Yazen.Ghannam@amd.com>
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for chip selects handling
> 
> On Tue, Jul 09, 2019 at 09:56:54PM +0000, Ghannam, Yazen wrote:
> > From: Yazen Ghannam <yazen.ghannam@amd.com>
> >
> > The struct chip_select array that's used for saving chip select bases
> > and masks is fixed at length of two. There should be one struct
> > chip_select for each controller, so this array should be increased to
> > support systems that may have more than two controllers.
> >
> > Increase the size of the struct chip_select array to eight, which is the
> > largest number of controllers per die currently supported on AMD
> > systems.
> >
> > Fix number of DIMMs and Chip Select bases/masks on Family17h, because AMD
> > Family 17h systems support 2 DIMMs, 4 CS bases, and 2 CS masks per
> > channel.
> >
> > Also, carve out the Family 17h+ reading of the bases/masks into a
> > separate function. This effectively reverts the original bases/masks
> > reading code to before Family 17h support was added.
> >
> > This is a second version of a commit that was reverted.
> >
> > Fixes: 07ed82ef93d6 ("EDAC, amd64: Add Fam17h debug output")
> > Fixes: 8de9930a4618 ("Revert "EDAC/amd64: Support more than two controllers for chip select handling"")
> 
> I'm not sure about those Fixes: tags you're slapping everywhere. First
> of all, 8de9930a4618 is a revert so how can this be fixing a revert? If
> anything, it should be fixing the original commit
> 
>   0a227af521d6 ("EDAC/amd64: Support more than two controllers for chip select handling")
> 
> which tried the more-than-2-memory-controllers thing.
> 
> But, it is not really a fix for that commit but a second attempt at it.
> Which is not really a fix but hw enablement.
> 
> So I'm dropping those tags here. If you want them in stable, pls
> backport them properly and test them on the respective stable kernels
> before sending them to stable.
> 

Okay, no problem.

Should I drop the Fixes tags on any other of the patches in this set?

Thanks,
Yazen

  reply	other threads:[~2019-08-19 19:56 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-09 21:56 [PATCH v2 0/7] AMD64 EDAC fixes Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for chip selects handling Ghannam, Yazen
2019-07-10 16:54   ` Phillips, Kim
2019-08-02  6:49   ` Borislav Petkov
2019-08-19 19:55     ` Ghannam, Yazen [this message]
2019-07-09 21:56 ` [PATCH v2 3/7] EDAC/amd64: Initialize DIMM info for systems with more than two channels Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 2/7] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP Ghannam, Yazen
2019-08-02  7:42   ` Borislav Petkov
2019-08-19 20:19     ` Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 4/7] EDAC/amd64: Find Chip Select memory size using Address Mask Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 6/7] EDAC/amd64: Cache secondary Chip Select registers Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 5/7] EDAC/amd64: Decode syndrome before translating address Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 7/7] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs Ghannam, Yazen
2019-08-02 14:46 ` [PATCH v2 0/7] AMD64 EDAC fixes Borislav Petkov
2019-08-15 20:08   ` Ghannam, Yazen
2019-08-16  6:47     ` Borislav Petkov

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