From: Satya Tangirala <satyat@google.com>
To: Eric Biggers <ebiggers@kernel.org>
Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-fscrypt@vger.kernel.org,
Ulf Hansson <ulf.hansson@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Asutosh Das <asutoshd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Neeraj Soni <neersoni@codeaurora.org>,
Barani Muthukumaran <bmuthuku@codeaurora.org>,
Peng Zhou <peng.zhou@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>,
Konrad Dybcio <konradybcio@gmail.com>
Subject: Re: [PATCH v2 5/9] mmc: cqhci: add cqhci_host_ops::program_key
Date: Tue, 8 Dec 2020 23:48:11 +0000 [thread overview]
Message-ID: <X9AQu2EhgG9znKY+@google.com> (raw)
In-Reply-To: <20201203020516.225701-6-ebiggers@kernel.org>
On Wed, Dec 02, 2020 at 06:05:12PM -0800, Eric Biggers wrote:
> From: Eric Biggers <ebiggers@google.com>
>
> On Snapdragon SoCs, the Linux kernel isn't permitted to directly access
> the standard CQHCI crypto configuration registers. Instead, programming
> and evicting keys must be done through vendor-specific SMC calls.
>
> To support this hardware, add a ->program_key() method to
> 'struct cqhci_host_ops'. This allows overriding the standard CQHCI
> crypto key programming / eviction procedure.
>
> This is inspired by the corresponding UFS crypto support, which uses
> these same SMC calls. See commit 1bc726e26ef3 ("scsi: ufs: Add
> program_key() variant op").
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> Signed-off-by: Eric Biggers <ebiggers@google.com>
> ---
> drivers/mmc/host/cqhci-crypto.c | 22 +++++++++++++---------
> drivers/mmc/host/cqhci.h | 4 ++++
> 2 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c
> index 98f141c8480ce..0aaa948d240b1 100644
> --- a/drivers/mmc/host/cqhci-crypto.c
> +++ b/drivers/mmc/host/cqhci-crypto.c
> @@ -30,13 +30,16 @@ cqhci_host_from_ksm(struct blk_keyslot_manager *ksm)
> return mmc->cqe_private;
> }
>
> -static void cqhci_crypto_program_key(struct cqhci_host *cq_host,
> - const union cqhci_crypto_cfg_entry *cfg,
> - int slot)
> +static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
> + const union cqhci_crypto_cfg_entry *cfg,
> + int slot)
> {
> u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
> int i;
>
> + if (cq_host->ops->program_key)
> + return cq_host->ops->program_key(cq_host, cfg, slot);
> +
> /* Clear CFGE */
> cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
>
> @@ -51,6 +54,7 @@ static void cqhci_crypto_program_key(struct cqhci_host *cq_host,
> /* Write dword 16, which includes the new value of CFGE */
> cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
> slot_offset + 16 * sizeof(cfg->reg_val[0]));
> + return 0;
> }
>
> static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
> @@ -67,6 +71,7 @@ static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
> int i;
> int cap_idx = -1;
> union cqhci_crypto_cfg_entry cfg = {};
> + int err;
>
> BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
> for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
> @@ -93,13 +98,13 @@ static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
> memcpy(cfg.crypto_key, key->raw, key->size);
> }
>
> - cqhci_crypto_program_key(cq_host, &cfg, slot);
> + err = cqhci_crypto_program_key(cq_host, &cfg, slot);
>
> memzero_explicit(&cfg, sizeof(cfg));
> - return 0;
> + return err;
> }
>
> -static void cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
> +static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
> {
> /*
> * Clear the crypto cfg on the device. Clearing CFGE
> @@ -107,7 +112,7 @@ static void cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
> */
> union cqhci_crypto_cfg_entry cfg = {};
>
> - cqhci_crypto_program_key(cq_host, &cfg, slot);
> + return cqhci_crypto_program_key(cq_host, &cfg, slot);
> }
>
> static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
> @@ -116,8 +121,7 @@ static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
> {
> struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
>
> - cqhci_crypto_clear_keyslot(cq_host, slot);
> - return 0;
> + return cqhci_crypto_clear_keyslot(cq_host, slot);
> }
>
> /*
> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> index 5c18734624fea..ece997dd8bcc7 100644
> --- a/drivers/mmc/host/cqhci.h
> +++ b/drivers/mmc/host/cqhci.h
> @@ -287,6 +287,10 @@ struct cqhci_host_ops {
> u64 *data);
> void (*pre_enable)(struct mmc_host *mmc);
> void (*post_disable)(struct mmc_host *mmc);
> +#ifdef CONFIG_MMC_CRYPTO
> + int (*program_key)(struct cqhci_host *cq_host,
> + const union cqhci_crypto_cfg_entry *cfg, int slot);
> +#endif
> };
>
> static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
> --
> 2.29.2
>
Looks good to me. Please feel free to add
Reviewed-by: Satya Tangirala <satyat@google.com>
next prev parent reply other threads:[~2020-12-08 23:48 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-03 2:05 [PATCH v2 0/9] eMMC inline encryption support Eric Biggers
2020-12-03 2:05 ` [PATCH v2 1/9] mmc: add basic support for inline encryption Eric Biggers
2020-12-08 23:40 ` Satya Tangirala
2020-12-03 2:05 ` [PATCH v2 2/9] mmc: cqhci: rename cqhci.c to cqhci-core.c Eric Biggers
2020-12-03 2:05 ` [PATCH v2 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors Eric Biggers
2020-12-03 6:45 ` Adrian Hunter
2020-12-03 19:23 ` Eric Biggers
2020-12-08 23:45 ` Satya Tangirala
2020-12-03 2:05 ` [PATCH v2 4/9] mmc: cqhci: add support for inline encryption Eric Biggers
2020-12-03 6:47 ` Adrian Hunter
2020-12-05 10:59 ` Satya Tangirala
2020-12-05 12:33 ` Satya Tangirala
2020-12-05 18:20 ` Eric Biggers
2020-12-05 12:28 ` Satya Tangirala
2020-12-05 18:07 ` Eric Biggers
2020-12-09 0:01 ` Satya Tangirala
2020-12-03 2:05 ` [PATCH v2 5/9] mmc: cqhci: add cqhci_host_ops::program_key Eric Biggers
2020-12-08 23:48 ` Satya Tangirala [this message]
2020-12-03 2:05 ` [PATCH v2 6/9] firmware: qcom_scm: update comment for ICE-related functions Eric Biggers
2020-12-08 23:52 ` Satya Tangirala
2020-12-03 2:05 ` [PATCH v2 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock Eric Biggers
2020-12-08 23:54 ` Satya Tangirala
2020-12-03 2:05 ` [PATCH v2 8/9] arm64: dts: qcom: sdm630: add ICE registers and clocks Eric Biggers
2020-12-03 2:05 ` [PATCH v2 9/9] mmc: sdhci-msm: add Inline Crypto Engine support Eric Biggers
2020-12-03 6:51 ` Adrian Hunter
2020-12-05 12:09 ` Satya Tangirala
2020-12-05 19:43 ` Eric Biggers
2020-12-08 23:58 ` Satya Tangirala
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=X9AQu2EhgG9znKY+@google.com \
--to=satyat@google.com \
--cc=adrian.hunter@intel.com \
--cc=agross@kernel.org \
--cc=asutoshd@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=bmuthuku@codeaurora.org \
--cc=devicetree@vger.kernel.org \
--cc=ebiggers@kernel.org \
--cc=konradybcio@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-fscrypt@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=neersoni@codeaurora.org \
--cc=peng.zhou@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=stanley.chu@mediatek.com \
--cc=ulf.hansson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).