From: Christian Eggers <ceggers@arri.de>
To: David Laight <David.Laight@aculab.com>
Cc: "Oleksij Rempel" <linux@rempel-privat.de>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"NXP Linux Team" <linux-imx@nxp.com>,
"linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"Krzysztof Kozlowski" <krzk@kernel.org>
Subject: Re: [PATCH v3 1/3] i2c: imx: Fix reset of I2SR_IAL flag
Date: Tue, 6 Oct 2020 14:30:55 +0200 [thread overview]
Message-ID: <2080355.2eSLTprjVn@n95hx1g2> (raw)
In-Reply-To: <f8f1a9f54e0e426dbe27cc13a3b9de8d@AcuMS.aculab.com>
Hi David,
On Tuesday, 6 October 2020, 14:06:36 CEST, David Laight wrote:
> From: Christian Eggers
> > +static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned
> > int bits) +{
> > + unsigned int temp;
> > +
> > + /*
> > + * i2sr_clr_opcode is the value to clear all interrupts.
> > + * Here we want to clear only <bits>, so we write
> > + * ~i2sr_clr_opcode with just <bits> toggled.
> > + */
> > + temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
> > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
> > +}
>
> That looks either wrong or maybe just overcomplicated.
Yes, it looks so.
> Why isn't:
> imx_i2c_write_reg(bits, i2c_imx, IMX_I2C_I2SR);
> enough?
i.MX requires W1C and Vybrid requires W0C in order to clear status bits.
> More usually you just write back the read value of such
> 'write 1 to clear' status registers and then act on all
> the set bits.
This pattern has been suggested by Uwe Klein-Koenig. It works because write
access to read-only register bits is ignored, independent whether 0 or 1 is
written. W0C is quite unusual, but I didn't design the hardware... The pattern
ensures that not accidentally more status bits are cleared than desired.
> That ensures you clear all interrupts that were pending.
I think that Uwe's intention was not clearing bits which are not handled at
this place. Otherwise events may get lost.
> If you need to avoid writes of bits that aren't in the
> 'clear all interrupts' value then you just need:
> bits &= i2c_imx->hwdata->i2sr_clr_opcode;
> prior to the write.
I think this wouldn't fit the W0C case for Vybrid.
Best regards
Christian
next prev parent reply other threads:[~2020-10-06 12:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-02 15:23 [PATCH v2 0/3] i2c: imx: Fix handling of arbitration loss Christian Eggers
2020-10-02 15:23 ` [PATCH v2 1/3] i2c: imx: Fix reset of I2SR_IAL flag Christian Eggers
2020-10-05 8:05 ` Krzysztof Kozlowski
2020-10-06 6:05 ` Uwe Kleine-König
2020-10-06 10:51 ` [PATCH v3 0/3] i2c: imx: Fix handling of arbitration loss Christian Eggers
2020-10-06 10:51 ` [PATCH v3 1/3] i2c: imx: Fix reset of I2SR_IAL flag Christian Eggers
2020-10-06 12:06 ` David Laight
2020-10-06 12:30 ` Christian Eggers [this message]
2020-10-06 12:46 ` Uwe Kleine-König
2020-10-06 12:52 ` David Laight
2020-10-06 10:51 ` [PATCH v3 2/3] i2c: imx: Check for I2SR_IAL after every byte Christian Eggers
2020-10-06 10:51 ` [PATCH v3 3/3] i2c: imx: Don't generate STOP condition if arbitration has been lost Christian Eggers
2020-10-02 15:23 ` [PATCH v2 2/3] i2c: imx: Check for I2SR_IAL after every byte Christian Eggers
2020-10-05 8:07 ` Krzysztof Kozlowski
2020-10-05 9:25 ` Christian Eggers
2020-10-02 15:23 ` [PATCH v2 3/3] i2c: imx: Don't generate STOP condition if arbitration has been lost Christian Eggers
2020-10-05 8:16 ` Krzysztof Kozlowski
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