From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C77C433ED for ; Thu, 1 Apr 2021 18:45:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F2BC66100A for ; Thu, 1 Apr 2021 18:45:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235093AbhDASpO (ORCPT ); Thu, 1 Apr 2021 14:45:14 -0400 Received: from mga17.intel.com ([192.55.52.151]:21588 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239257AbhDASfj (ORCPT ); Thu, 1 Apr 2021 14:35:39 -0400 IronPort-SDR: tXO/dxmlE5sqd1abhq/7nn/2XptM3h5IpMnQ6tsBCsPJRlAOfWs3a87FqDV+pmd6RLyHt4oF/i jaEYdmYFPIJg== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="172302385" X-IronPort-AV: E=Sophos;i="5.81,296,1610438400"; d="scan'208";a="172302385" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 08:45:09 -0700 IronPort-SDR: 9JIoGX7euufyX4xQWwr0Nz8ALNgrGaxn0Oao/n8CFrYiEl1uSjPYxQOBJdkMAJKtCd5w6N1DlZ 2Mm0sBPNEIiQ== X-IronPort-AV: E=Sophos;i="5.81,296,1610438400"; d="scan'208";a="377743107" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 08:45:05 -0700 Received: from andy by smile with local (Exim 4.94) (envelope-from ) id 1lRzVG-000IET-2U; Thu, 01 Apr 2021 18:45:02 +0300 Date: Thu, 1 Apr 2021 18:45:02 +0300 From: Andy Shevchenko To: Henning Schild Cc: Bjorn Helgaas , Wolfram Sang , Jean Delvare , Lee Jones , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, Jean Delvare , Peter Tyser , hdegoede@redhat.com Subject: Re: [PATCH v1 3/7] PCI: New Primary to Sideband (P2SB) bridge support library Message-ID: References: <20210309014221.GA1831206@bjorn-Precision-5520> <20210309094252.396b7f2d@md1za8fc.ad001.siemens.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210309094252.396b7f2d@md1za8fc.ad001.siemens.net> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org On Tue, Mar 09, 2021 at 09:42:52AM +0100, Henning Schild wrote: > Am Mon, 8 Mar 2021 19:42:21 -0600 > schrieb Bjorn Helgaas : > > On Mon, Mar 08, 2021 at 09:16:50PM +0200, Andy Shevchenko wrote: > > > On Mon, Mar 08, 2021 at 12:52:12PM -0600, Bjorn Helgaas wrote: > > > > On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote: ... > > > > > + /* Read the first BAR of the device in question */ > > > > > + __pci_bus_read_base(bus, devfn, pci_bar_unknown, mem, > > > > > PCI_BASE_ADDRESS_0, true); > > > > > > > > I don't get this. Apparently this normally hidden device is > > > > consuming PCI address space. The PCI core needs to know about > > > > this. If it doesn't, the PCI core may assign this space to > > > > another device. > > > > > > Right, it returns all 1:s to any request so PCI core *thinks* it's > > > plugged off (like D3cold or so). > > > > I'm asking about the MMIO address space. The BAR is a register in > > config space. AFAICT, clearing P2SBC_HIDE_BYTE makes that BAR > > visible. The BAR describes a region of PCI address space. It looks > > like setting P2SBC_HIDE_BIT makes the BAR disappear from config space, > > but it sounds like the PCI address space *described* by the BAR is > > still claimed by the device. If the device didn't respond to that > > MMIO space, you would have no reason to read the BAR at all. > > > > So what keeps the PCI core from assigning that MMIO space to another > > device? > > The device will respond to MMIO while being hidden. I am afraid nothing > stops a collision, except for the assumption that the BIOS is always > right and PCI devices never get remapped. But just guessing here. > > I have seen devices with coreboot having the P2SB visible, and most > likely relocatable. Making it visible in Linux and not hiding it again > might work, but probably only as long as Linux will not relocate it. > Which i am afraid might seriously upset the BIOS, depending on what a > device does with those GPIOs and which parts are implemented in the > BIOS. So the question is, do we have knobs in PCI core to mark device fixes in terms of BARs, no relocation must be applied, no other devices must have the region? -- With Best Regards, Andy Shevchenko