From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 464C9C433FE for ; Fri, 26 Nov 2021 15:12:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354121AbhKZPP5 (ORCPT ); Fri, 26 Nov 2021 10:15:57 -0500 Received: from mga18.intel.com ([134.134.136.126]:47878 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354128AbhKZPN4 (ORCPT ); Fri, 26 Nov 2021 10:13:56 -0500 X-IronPort-AV: E=McAfee;i="6200,9189,10179"; a="222548406" X-IronPort-AV: E=Sophos;i="5.87,266,1631602800"; d="scan'208";a="222548406" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2021 07:10:43 -0800 X-IronPort-AV: E=Sophos;i="5.87,266,1631602800"; d="scan'208";a="457703842" Received: from smile.fi.intel.com ([10.237.72.184]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2021 07:10:40 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.95) (envelope-from ) id 1mqcs1-00Aogm-Ii; Fri, 26 Nov 2021 17:10:37 +0200 Date: Fri, 26 Nov 2021 17:10:37 +0200 From: Andy Shevchenko To: Bjorn Helgaas Cc: Henning Schild , Wolfram Sang , Jean Delvare , Lee Jones , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, Jean Delvare , Peter Tyser , hdegoede@redhat.com Subject: Re: [PATCH v1 3/7] PCI: New Primary to Sideband (P2SB) bridge support library Message-ID: References: <20210401184446.GA1528755@bjorn-Precision-5520> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org On Mon, Jul 12, 2021 at 03:15:17PM +0300, Andy Shevchenko wrote: > On Thu, Apr 01, 2021 at 01:44:46PM -0500, Bjorn Helgaas wrote: > > On Thu, Apr 01, 2021 at 09:23:04PM +0300, Andy Shevchenko wrote: > > > On Thu, Apr 01, 2021 at 11:42:56AM -0500, Bjorn Helgaas wrote: > > > > On Thu, Apr 01, 2021 at 06:45:02PM +0300, Andy Shevchenko wrote: > > > > > On Tue, Mar 09, 2021 at 09:42:52AM +0100, Henning Schild wrote: > > > > > > Am Mon, 8 Mar 2021 19:42:21 -0600 > > > > > > schrieb Bjorn Helgaas : > > > > > > > On Mon, Mar 08, 2021 at 09:16:50PM +0200, Andy Shevchenko wrote: > > > > > > > > On Mon, Mar 08, 2021 at 12:52:12PM -0600, Bjorn Helgaas wrote: > > > > > > > > > On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote: > > > > > > > > > > ... > > > > > > > > > > > > > > > + /* Read the first BAR of the device in question */ > > > > > > > > > > + __pci_bus_read_base(bus, devfn, pci_bar_unknown, mem, > > > > > > > > > > PCI_BASE_ADDRESS_0, true); > > > > > > > > > > > > > > > > > > I don't get this. Apparently this normally hidden device is > > > > > > > > > consuming PCI address space. The PCI core needs to know > > > > > > > > > about this. If it doesn't, the PCI core may assign this > > > > > > > > > space to another device. > > > > > > > > > > > > > > > > Right, it returns all 1:s to any request so PCI core *thinks* > > > > > > > > it's plugged off (like D3cold or so). > > > > > > > > > > > > > > I'm asking about the MMIO address space. The BAR is a register > > > > > > > in config space. AFAICT, clearing P2SBC_HIDE_BYTE makes that > > > > > > > BAR visible. The BAR describes a region of PCI address space. > > > > > > > It looks like setting P2SBC_HIDE_BIT makes the BAR disappear > > > > > > > from config space, but it sounds like the PCI address space > > > > > > > *described* by the BAR is still claimed by the device. If the > > > > > > > device didn't respond to that MMIO space, you would have no > > > > > > > reason to read the BAR at all. > > > > > > > > > > > > > > So what keeps the PCI core from assigning that MMIO space to > > > > > > > another device? > > > > > > > > > > > > The device will respond to MMIO while being hidden. I am afraid > > > > > > nothing stops a collision, except for the assumption that the BIOS > > > > > > is always right and PCI devices never get remapped. But just > > > > > > guessing here. > > > > > > > > > > > > I have seen devices with coreboot having the P2SB visible, and > > > > > > most likely relocatable. Making it visible in Linux and not hiding > > > > > > it again might work, but probably only as long as Linux will not > > > > > > relocate it. Which i am afraid might seriously upset the BIOS, > > > > > > depending on what a device does with those GPIOs and which parts > > > > > > are implemented in the BIOS. > > > > > > > > > > So the question is, do we have knobs in PCI core to mark device > > > > > fixes in terms of BARs, no relocation must be applied, no other > > > > > devices must have the region? > > > > > > > > I think the closest thing is the IORESOURCE_PCI_FIXED bit that we use > > > > for things that must not be moved. Generally PCI resources are > > > > associated with a pci_dev, and we set IORESOURCE_PCI_FIXED for BARs, > > > > e.g., dev->resource[n]. We do that for IDE legacy regions (see > > > > LEGACY_IO_RESOURCE), Langwell devices (pci_fixed_bar_fixup()), > > > > "enhanced allocation" (pci_ea_flags()), and some quirks (quirk_io()). > > > > > > > > In your case, the device is hidden so it doesn't respond to config > > > > accesses, so there is no pci_dev for it. > > > > > > Yes, and the idea is to unhide it on the early stage. > > > Would it be possible to quirk it to fix the IO resources? > > > > If I read your current patch right, it unhides the device, reads the > > BAR, then hides the device again. I didn't see that it would create a > > pci_dev for it. > > > > If you unhide it and then enumerate it normally (and mark the BAR as > > IORESOURCE_PCI_FIXED to make sure we never move it), that might work. > > Then there should be a pci_dev for it, and it would then show up in > > sysfs, lspci, etc. And we should insert the BAR in iomem_resource, so > > we should see it in /proc/iomem and we won't accidentally put > > something else on top of it. > > If the PCI device is present and we have ACPI description for the one or more > devices (currently pin control), wouldn't be a conflicting resources issue? > > When would be the suitable place to avoid that? Given another thought on that and I think we can't unhide entire P2SB due to possible ACPI tables present which may or may not fully or partially describe devices behind that bridge, so, I would stick with current approach. > > > > resource, fills it in, sets IORESOURCE_PCI_FIXED, and does something > > > > similar to pci_claim_resource()? -- With Best Regards, Andy Shevchenko