Re: [PATCH V5 3/5] iio: adc: Add support for PMIC7 ADC

From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Jishnu Prakash <jprakash@codeaurora.org>
Cc: agross@kernel.org, Bjorn Andersson <bjorn.andersson@linaro.org>,
	devicetree <devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Matthias Kaehlcke <mka@chromium.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Amit Kucheria <amit.kucheria@verdurent.com>,
	smohanad@codeaurora.org, kgunda@codeaurora.org,
	aghayal@codeaurora.org, Jonathan Cameron <jic23@kernel.org>,
	Hartmut Knaack <knaack.h@gmx.de>,
	Lars-Peter Clausen <lars@metafoo.de>,
	Peter Meerwald-Stadler <pmeerw@pmeerw.net>,
	linux-arm-msm@vger.kernel.org,
	linux-iio <linux-iio@vger.kernel.org>,
	linux-arm-msm-owner@vger.kernel.org
Subject: Re: [PATCH V5 3/5] iio: adc: Add support for PMIC7 ADC
Date: Fri, 22 May 2020 18:37:55 +0300	[thread overview]
Message-ID: <CAHp75Vfgk0-Rye2We1A6_WTWMCK3D-WW4_T3CGPHc=-tB=6M9g@mail.gmail.com> (raw)
In-Reply-To: <1590157452-27179-4-git-send-email-jprakash@codeaurora.org>

On Fri, May 22, 2020 at 5:25 PM Jishnu Prakash <jprakash@codeaurora.org> wrote:
>
> The ADC architecture on PMIC7 is changed as compared to PMIC5. The
> major change from PMIC5 is that all SW communication to ADC goes through
> PMK8350, which communicates with other PMICs through PBS when the ADC
> on PMK8350 works in master mode. The SID register is used to identify the
> PMICs with which the PBS needs to communicate. Add support for the same.

Below should be in a separate patch, but it's a bikeshedding. So, I
left it to maintainers to decide.
Fine with me
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

...

> @@ -285,7 +304,7 @@ static int adc5_configure(struct adc5_chip *adc,
>
>         /* Read registers 0x42 through 0x46 */
>         ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
> -       if (ret < 0)
> +       if (ret)
>                 return ret;
>
>         /* Digital param selection */

...

> @@ -331,7 +391,7 @@ static int adc5_do_conversion(struct adc5_chip *adc,
>
>         if (adc->poll_eoc) {
>                 ret = adc5_poll_wait_eoc(adc);
> -               if (ret < 0) {
> +               if (ret) {
>                         pr_err("EOC bit not set\n");
>                         goto unlock;
>                 }
> @@ -341,7 +401,7 @@ static int adc5_do_conversion(struct adc5_chip *adc,
>                 if (!ret) {
>                         pr_debug("Did not get completion timeout.\n");
>                         ret = adc5_poll_wait_eoc(adc);
> -                       if (ret < 0) {
> +                       if (ret) {
>                                 pr_err("EOC bit not set\n");
>                                 goto unlock;
>                         }

...

> @@ -406,8 +519,38 @@ static int adc5_read_raw(struct iio_dev *indio_dev,
>         default:
>                 return -EINVAL;
>         }
> +}
>
> -       return 0;

(this one looks like standalone change from above)

...

> @@ -570,7 +762,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc,
>
>                 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
>                                                         sizeof(dig_version));
> -               if (ret < 0) {
> +               if (ret) {
>                         dev_err(dev, "Invalid dig version read %d\n", ret);
>                         return ret;
>                 }

...

> +       if (of_device_is_compatible(node, "qcom,spmi-adc7"))
> +               indio_dev->info = &adc7_info;
> +       else
> +               indio_dev->info = &adc5_info;

Can we use driver_data?

...

> +       if (adcmap7_die_temp[0].x > voltage) {
> +               *result_mdec = DIE_TEMP_ADC7_SCALE_1;
> +               return 0;

> +       } else if (adcmap7_die_temp[i].x <= voltage) {

As per previous comment, redundant 'else' and please use value of i
directly here.

-- 
With Best Regards,
Andy Shevchenko