From: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, thomasz@nvidia.com, jtukkinen@nvidia.com,
mperttunen@nvidia.com, will@kernel.org,
linux-kernel@vger.kernel.org, praithatha@nvidia.com,
talho@nvidia.com, iommu@lists.linux-foundation.org,
linux-tegra@vger.kernel.org, yhsu@nvidia.com, treding@nvidia.com,
robin.murphy@arm.com, avanbrunt@nvidia.com,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/7] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU
Date: Mon, 2 Sep 2019 20:32:04 -0700 [thread overview]
Message-ID: <1567481528-31163-4-git-send-email-vdumpa@nvidia.com> (raw)
In-Reply-To: <1567481528-31163-1-git-send-email-vdumpa@nvidia.com>
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3b..1d72fac 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -31,6 +31,10 @@ conditions.
as below, SoC-specific compatibles:
"qcom,sdm845-smmu-500", "arm,mmu-500"
+ NVIDIA SoCs that use more than one ARM MMU-500 together
+ needs following SoC-specific compatibles along with "arm,mmu-500":
+ "nvidia,tegra194-smmu"
+
- reg : Base address and size of the SMMU.
- #global-interrupts : The number of global interrupts exposed by the
--
2.1.4
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2019-09-03 3:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 3:32 [PATCH v2 0/7] Nvidia Arm SMMUv2 Implementation Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 1/7] iommu/arm-smmu: prepare arm_smmu_flush_ops for override Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 2/7] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Krishna Reddy
2019-09-03 3:32 ` Krishna Reddy [this message]
2019-09-03 3:32 ` [PATCH v2 4/7] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 5/7] arm64: tegra: Add Memory controller DT node on T194 Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 6/7] arm64: tegra: Add DT node for T194 SMMU Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 7/7] arm64: tegra: enable SMMU for SDHCI and EQOS on T194 Krishna Reddy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1567481528-31163-4-git-send-email-vdumpa@nvidia.com \
--to=vdumpa@nvidia.com \
--cc=avanbrunt@nvidia.com \
--cc=iommu@lists.linux-foundation.org \
--cc=jtukkinen@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mperttunen@nvidia.com \
--cc=praithatha@nvidia.com \
--cc=robin.murphy@arm.com \
--cc=snikam@nvidia.com \
--cc=talho@nvidia.com \
--cc=thomasz@nvidia.com \
--cc=treding@nvidia.com \
--cc=will@kernel.org \
--cc=yhsu@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).