From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Philippe Brucker Subject: [PATCH v2 40/40] iommu/arm-smmu-v3: Add support for PCI PASID Date: Fri, 11 May 2018 20:06:41 +0100 Message-ID: <20180511190641.23008-41-jean-philippe.brucker@arm.com> References: <20180511190641.23008-1-jean-philippe.brucker@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180511190641.23008-1-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org Cc: xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org, rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, christian.koenig-5C7GfCeVMHo@public.gmane.org List-Id: iommu@lists.linux-foundation.org Enable PASID for PCI devices that support it. Unlike PRI, we can't enable PASID lazily in iommu_sva_device_init(), because it has to be enabled before ATS, and because we have to allocate substream tables early. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 0edbb8d19579..ac6e69f25893 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2542,6 +2542,52 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) return sid < limit; } +static int arm_smmu_enable_pasid(struct arm_smmu_master_data *master) +{ + int ret; + int features; + u8 pasid_bits; + int num_pasids; + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return -ENOSYS; + + pdev = to_pci_dev(master->dev); + + features = pci_pasid_features(pdev); + if (features < 0) + return -ENOSYS; + + num_pasids = pci_max_pasids(pdev); + if (num_pasids <= 0) + return -ENOSYS; + + pasid_bits = min_t(u8, ilog2(num_pasids), master->smmu->ssid_bits); + + dev_dbg(&pdev->dev, "device supports %#x PASID bits [%s%s]\n", pasid_bits, + (features & PCI_PASID_CAP_EXEC) ? "x" : "", + (features & PCI_PASID_CAP_PRIV) ? "p" : ""); + + ret = pci_enable_pasid(pdev, features); + return ret ? ret : pasid_bits; +} + +static void arm_smmu_disable_pasid(struct arm_smmu_master_data *master) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return; + + pdev = to_pci_dev(master->dev); + + if (!pdev->pasid_enabled) + return; + + pci_disable_pasid(pdev); +} + static int arm_smmu_enable_ats(struct arm_smmu_master_data *master) { size_t stu; @@ -2712,6 +2758,11 @@ static int arm_smmu_add_device(struct device *dev) master->ste.can_stall = true; } + /* PASID must be enabled before ATS */ + ret = arm_smmu_enable_pasid(master); + if (ret > 0) + master->ssid_bits = ret; + arm_smmu_enable_ats(master); ret = iommu_device_link(&smmu->iommu, dev); @@ -2740,6 +2791,7 @@ static int arm_smmu_add_device(struct device *dev) err_disable_ats: arm_smmu_disable_ats(master); + arm_smmu_disable_pasid(master); err_free_master: kfree(master); @@ -2769,7 +2821,9 @@ static void arm_smmu_remove_device(struct device *dev) arm_smmu_remove_master(smmu, master); iommu_device_unlink(&smmu->iommu, dev); arm_smmu_disable_pri(master); + /* PASID must be disabled after ATS */ arm_smmu_disable_ats(master); + arm_smmu_disable_pasid(master); kfree(master); iommu_fwspec_free(dev); } -- 2.17.0