From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org
Cc: devicetree@vger.kernel.org, "Jason Cooper" <jason@lakedaemon.net>,
"Andrew Lunn" <andrew@lunn.ch>,
"Antoine Tenart" <antoine.tenart@bootlin.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>,
"Will Deacon" <will.deacon@arm.com>,
"Maxime Chevallier" <maxime.chevallier@bootlin.com>,
"Nadav Haklai" <nadavh@marvell.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Miquèl Raynal" <miquel.raynal@bootlin.com>,
"Hanna Hawa" <hannah@marvell.com>,
linux-arm-kernel@lists.infradead.org,
"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>
Subject: [PATCH v2 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743
Date: Thu, 11 Jul 2019 17:02:40 +0200 [thread overview]
Message-ID: <20190711150242.25290-3-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20190711150242.25290-1-gregory.clement@bootlin.com>
From: Hanna Hawa <hannah@marvell.com>
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
We also mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format but
only AARCH32_L. Indeed with AArch64 format 32 bits acces is not
supported.
Note that separate writes/reads to 2 is not problem regards to
atomicity, because the driver use the readq/writeq while initialize
the SMMU, report for SMMU fault, and use spinlock in one
case (iova_to_phys).
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/arm64/silicon-errata.txt | 2 ++
drivers/iommu/arm-smmu.c | 42 +++++++++++++++++++++++---
2 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index d1e2bb801e1b..3f78ae7a7690 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -72,6 +72,8 @@ stable kernels.
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
+| Marvell | ARM-MMU-500 | #582743 | N/A |
+| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ac0784b5b675..32536ccae22d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -126,6 +126,7 @@ enum arm_smmu_arch_version {
enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
+ MRVL_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
};
@@ -301,13 +302,35 @@ static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
u64 val,
void __iomem *addr)
{
- writeq_relaxed(val, addr);
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the writeq to double writel
+ */
+ if (smmu->model != MRVL_MMU500) {
+ writeq_relaxed(val, addr);
+ return;
+ }
+
+ writel_relaxed(upper_32_bits(val), addr + 4);
+ writel_relaxed(lower_32_bits(val), addr);
}
static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
void __iomem *addr)
{
- return readq_relaxed(addr);
+ u64 val;
+
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the readq to double readl
+ */
+ if (smmu->model != MRVL_MMU500)
+ return readq_relaxed(addr);
+
+ val = (u64)readl_relaxed(addr + 4) << 32;
+ val |= readl_relaxed(addr);
+
+ return val;
}
static void parse_driver_options(struct arm_smmu_device *smmu)
@@ -1741,7 +1764,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
for (i = 0; i < smmu->num_mapping_groups; ++i)
arm_smmu_write_sme(smmu, i);
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
/*
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
@@ -1770,7 +1793,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
* Disable MMU-500's not-particularly-beneficial next-page
* prefetcher for the sake of errata #841119 and #826419.
*/
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
reg &= ~ARM_MMU500_ACTLR_CPRE;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
@@ -1987,6 +2010,15 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
if (id & ID2_VMID16)
smmu->features |= ARM_SMMU_FEAT_VMID16;
+ /*
+ * Armada-AP806 erratum #582743.
+ * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64
+ * formats altogether and allow using 32 bits access on the
+ * interconnect.
+ */
+ if (smmu->model == MRVL_MMU500)
+ id &= ~(ID2_PTFS_4K | ID2_PTFS_16K | ID2_PTFS_64K);
+
/*
* What the page table walker can address actually depends on which
* descriptor format is in use, but since a) we don't know that yet,
@@ -2053,6 +2085,7 @@ ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
+ARM_SMMU_MATCH_DATA(mrvl_mmu500, ARM_SMMU_V2, MRVL_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
@@ -2062,6 +2095,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
+ { .compatible = "marvell,mmu-500", .data = &mrvl_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
{ },
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2019-07-11 19:48 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-11 15:02 [PATCH v2 0/4] Add system mmu support for Armada-806 Gregory CLEMENT
2019-07-11 15:02 ` [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq Gregory CLEMENT
2019-08-20 12:08 ` Will Deacon
2019-08-22 14:30 ` Robin Murphy
2019-07-11 15:02 ` Gregory CLEMENT [this message]
2019-07-11 15:02 ` [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: add compatible string for Marvell Gregory CLEMENT
2019-07-24 20:36 ` [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: " Rob Herring
2019-08-22 14:16 ` [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: " Robin Murphy
2019-07-11 15:02 ` [PATCH v2 4/4] arm64: dts: marvell: armada-ap806: add smmu support Gregory CLEMENT
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190711150242.25290-3-gregory.clement@bootlin.com \
--to=gregory.clement@bootlin.com \
--cc=andrew@lunn.ch \
--cc=antoine.tenart@bootlin.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=hannah@marvell.com \
--cc=iommu@lists.linux-foundation.org \
--cc=jason@lakedaemon.net \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maxime.chevallier@bootlin.com \
--cc=miquel.raynal@bootlin.com \
--cc=nadavh@marvell.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=sebastian.hesselbarth@gmail.com \
--cc=thomas.petazzoni@bootlin.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).