From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>, Rob Herring <robh@kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Will Deacon <will@kernel.org>,
Steven Price <steven.price@arm.com>,
iommu@lists.linux-foundation.org,
Robin Murphy <robin.murphy@arm.com>
Subject: [PATCH AUTOSEL 5.3 04/99] iommu/io-pgtable-arm: Support all Mali configurations
Date: Sat, 26 Oct 2019 09:14:25 -0400 [thread overview]
Message-ID: <20191026131600.2507-4-sashal@kernel.org> (raw)
In-Reply-To: <20191026131600.2507-1-sashal@kernel.org>
From: Robin Murphy <robin.murphy@arm.com>
[ Upstream commit 1be08f458d1602275b02f5357ef069957058f3fd ]
In principle, Midgard GPUs supporting smaller VA sizes should only
require 3-level pagetables, since level 0 only resolves bits 48:40 of
the address. However, the kbase driver does not appear to have any
notion of a variable start level, and empirically T720 and T820 rapidly
blow up with translation faults unless given a full 4-level table,
despite only supporting a 33-bit VA size.
The 'real' IAS value is still valuable in terms of validating addresses
on map/unmap, so tweak the allocator to allow smaller values while still
forcing the resultant tables to the full 4 levels. As far as I can test,
this should make all known Midgard variants happy.
Fixes: d08d42de6432 ("iommu: io-pgtable: Add ARM Mali midgard MMU page table format")
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/iommu/io-pgtable-arm.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 9e35cd991f065..77f41c9dd9be7 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1022,7 +1022,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
if (cfg->quirks)
return NULL;
- if (cfg->ias != 48 || cfg->oas > 40)
+ if (cfg->ias > 48 || cfg->oas > 40)
return NULL;
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
@@ -1031,6 +1031,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
if (!data)
return NULL;
+ /* Mali seems to need a full 4-level table regardless of IAS */
+ if (data->levels < ARM_LPAE_MAX_LEVELS) {
+ data->levels = ARM_LPAE_MAX_LEVELS;
+ data->pgd_size = sizeof(arm_lpae_iopte);
+ }
/*
* MEMATTR: Mali has no actual notion of a non-cacheable type, so the
* best we can do is mimic the out-of-tree driver and hope that the
--
2.20.1
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next prev parent reply other threads:[~2019-10-26 13:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20191026131600.2507-1-sashal@kernel.org>
2019-10-26 13:14 ` [PATCH AUTOSEL 5.3 02/99] iommu/arm-smmu: Free context bitmap in the err path of arm_smmu_init_domain_context Sasha Levin
2019-10-26 13:14 ` [PATCH AUTOSEL 5.3 03/99] iommu/io-pgtable-arm: Correct Mali attributes Sasha Levin
2019-10-26 13:14 ` Sasha Levin [this message]
2019-10-26 13:15 ` [PATCH AUTOSEL 5.3 73/99] iommu/amd: Fix incorrect PASID decoding from event log Sasha Levin
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