From: Sebastian Ott via iommu <iommu@lists.linux-foundation.org>
To: Joerg Roedel <joro@8bytes.org>, <iommu@lists.linux-foundation.org>
Cc: Benjamin Serebrin <serebrin@amazon.com>,
Filippo Sironi <sironi@amazon.de>,
Sebastian Ott <sebott@amazon.de>
Subject: [PATCH 1/3] iommu/amd: Parse supported address sizes from IVRS
Date: Fri, 5 Jun 2020 16:56:53 +0200 [thread overview]
Message-ID: <20200605145655.13639-2-sebott@amazon.de> (raw)
In-Reply-To: <20200605145655.13639-1-sebott@amazon.de>
The IVRS ACPI table specifies maximum address sizes for I/O virtual
addresses that can be handled by the IOMMUs in the system. Parse that
data from the IVRS header so that it can be considered in limiting the
I/O aperture.
Based on prior work by Marius Hillenbrand.
Link: https://www.amd.com/system/files/TechDocs/48882_IOMMU_3.05_PUB.pdf
Signed-off-by: Sebastian Ott <sebott@amazon.de>
---
drivers/iommu/amd_iommu.c | 1 +
drivers/iommu/amd_iommu_init.c | 26 ++++++++++++++++++++++++++
drivers/iommu/amd_iommu_types.h | 3 +++
3 files changed, 30 insertions(+)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 2883ac389abb..fb4a44550c4a 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -88,6 +88,7 @@ const struct iommu_ops amd_iommu_ops;
static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
int amd_iommu_max_glx_val = -1;
+u8 amd_iommu_ivrs_va_size;
/*
* general struct to manage commands send to an IOMMU
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 5b81fd16f5fa..3b07218e7000 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -11,6 +11,7 @@
#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/list.h>
+#include <linux/bitfield.h>
#include <linux/bitmap.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
@@ -41,6 +42,7 @@
* definitions for the ACPI scanning code
*/
#define IVRS_HEADER_LENGTH 48
+#define IVRS_HEADER_IVINFO_OFFSET 36
#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
#define ACPI_IVMD_TYPE_ALL 0x20
@@ -2492,6 +2494,27 @@ static void __init free_dma_resources(void)
free_unity_maps();
}
+static void __init get_ivrs_ivinfo(struct acpi_table_header *ivrs)
+{
+ u32 *ivinfo = (u32 *)((u8 *)ivrs + IVRS_HEADER_IVINFO_OFFSET);
+ u8 va_size = FIELD_GET(GENMASK(21, 15), *ivinfo);
+ u8 valid_va_sizes[] = {32, 40, 48, 64};
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(valid_va_sizes); i++) {
+ if (va_size == valid_va_sizes[i]) {
+ amd_iommu_ivrs_va_size = va_size;
+ break;
+ }
+ }
+
+ if (!amd_iommu_ivrs_va_size) {
+ pr_warn("Invalid virtual address size %u in IVRS header, use most restrictive %u\n",
+ va_size, valid_va_sizes[0]);
+ amd_iommu_ivrs_va_size = valid_va_sizes[0];
+ }
+}
+
/*
* This is the hardware init function for AMD IOMMU in the system.
* This function is called either from amd_iommu_init or from the interrupt
@@ -2546,6 +2569,9 @@ static int __init early_amd_iommu_init(void)
if (ret)
goto out;
+ get_ivrs_ivinfo(ivrs_base);
+ DUMP_printk("IVRS vasize=%d\n", amd_iommu_ivrs_va_size);
+
amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 7a8fdec138bd..8141b2874170 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -755,6 +755,9 @@ extern bool amd_iommu_force_isolation;
/* Max levels of glxval supported */
extern int amd_iommu_max_glx_val;
+/* Maximum virtual address size supported */
+extern u8 amd_iommu_ivrs_va_size;
+
/*
* This function flushes all internal caches of
* the IOMMU used by this driver.
--
2.17.1
Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879
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next prev parent reply other threads:[~2020-06-05 18:00 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-05 14:56 [PATCH 0/3] iommu/amd: I/O VA address limits Sebastian Ott via iommu
2020-06-05 14:56 ` Sebastian Ott via iommu [this message]
2020-06-05 14:56 ` [PATCH 2/3] iommu/amd: Restrict aperture for domains to conform with IVRS Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 3/3] iommu/amd: Actually enforce geometry aperture Sebastian Ott via iommu
2020-06-30 9:30 ` Joerg Roedel
2020-06-30 22:46 ` [PATCH v2 0/3] iommu/amd: I/O VA address limits Sebastian Ott via iommu
2020-06-30 22:46 ` [PATCH v2 1/3] iommu/amd: Parse supported address sizes from IVRS Sebastian Ott via iommu
2020-06-30 22:46 ` [PATCH v2 2/3] iommu/amd: Restrict aperture for domains to conform with IVRS Sebastian Ott via iommu
2020-06-30 22:46 ` [PATCH v2 3/3] iommu/amd: Actually enforce geometry aperture Sebastian Ott via iommu
2020-07-10 12:31 ` [PATCH v2 0/3] iommu/amd: I/O VA address limits Joerg Roedel
2020-07-17 9:20 ` Sebastian Ott via iommu
2020-07-17 9:47 ` Robin Murphy
2020-07-17 13:22 ` Sironi, Filippo via iommu
2020-07-17 14:36 ` Robin Murphy
2020-07-17 15:15 ` Sironi, Filippo via iommu
2020-07-22 12:19 ` joro
2020-07-22 12:34 ` Sironi, Filippo via iommu
2020-07-22 14:00 ` joro
2020-06-24 16:09 ` [PATCH " Sebastian Ott via iommu
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