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From: Will Deacon <will@kernel.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Sean Paul <sean@poorly.run>,
	freedreno@lists.freedesktop.org, David Airlie <airlied@linux.ie>,
	linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org,
	linux-kernel@vger.kernel.org,
	Matthias Kaehlcke <mka@chromium.org>,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	dri-devel@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	Stephen Boyd <swboyd@chromium.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Sharat Masetty <smasetty@codeaurora.org>,
	linux-arm-kernel@lists.infradead.org,
	Emil Velikov <emil.velikov@collabora.com>
Subject: Re: [PATCHv3 7/7] drm/msm/a6xx: Add support for using system cache(LLC)
Date: Fri, 3 Jul 2020 16:40:26 +0100	[thread overview]
Message-ID: <20200703154025.GB19327@willie-the-truck> (raw)
In-Reply-To: <ecfda7ca80f6d7b4ff3d89b8758f4dc9@codeaurora.org>

On Fri, Jul 03, 2020 at 08:23:07PM +0530, Sai Prakash Ranjan wrote:
> On 2020-07-03 19:07, Will Deacon wrote:
> > On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
> > > diff --git a/drivers/gpu/drm/msm/msm_iommu.c
> > > b/drivers/gpu/drm/msm/msm_iommu.c
> > > index f455c597f76d..bd1d58229cc2 100644
> > > --- a/drivers/gpu/drm/msm/msm_iommu.c
> > > +++ b/drivers/gpu/drm/msm/msm_iommu.c
> > > @@ -218,6 +218,9 @@ static int msm_iommu_map(struct msm_mmu *mmu,
> > > uint64_t iova,
> > >  		iova |= GENMASK_ULL(63, 49);
> > > 
> > > 
> > > +	if (mmu->features & MMU_FEATURE_USE_SYSTEM_CACHE)
> > > +		prot |= IOMMU_SYS_CACHE_ONLY;
> > 
> > Given that I think this is the only user of IOMMU_SYS_CACHE_ONLY, then
> > it
> > looks like it should actually be a property on the domain because we
> > never
> > need to configure it on a per-mapping basis within a domain, and
> > therefore
> > it shouldn't be exposed by the IOMMU API as a prot flag.
> > 
> > Do you agree?
> > 
> 
> GPU being the only user is for now, but there are other clients which can
> use this.
> Plus how do we set the memory attributes if we do not expose this as prot
> flag?

I just don't understand the need for it to be per-map operation. Put another
way, if we extended the domain attribute to apply to cacheable mappings
on the domain and not just the table walk, what would break?

Will
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  reply	other threads:[~2020-07-03 15:40 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29 15:52 [PATCHv3 0/7] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 1/7] iommu/arm-smmu: Add a init_context_bank implementation hook Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 2/7] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for " Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 4/7] iommu: arm-smmu-impl: Remove unwanted extra blank lines Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 5/7] iommu: arm-smmu-impl: Convert to use of_match_node() for qcom impl Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 6/7] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 7/7] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-07-03 13:37   ` Will Deacon
2020-07-03 14:53     ` Sai Prakash Ranjan
2020-07-03 15:40       ` Will Deacon [this message]
2020-07-03 16:04       ` Rob Clark
2020-07-03 16:59         ` Sai Prakash Ranjan
2020-07-09 16:13         ` Jordan Crouse

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