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Thu, 09 Jul 2020 02:39:58 -0700 (PDT) Date: Thu, 9 Jul 2020 11:39:46 +0200 From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org Subject: Re: [PATCH v8 00/12] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part) Message-ID: <20200709093946.GC4477@myrica> References: <20200618155125.1548969-1-jean-philippe@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200618155125.1548969-1-jean-philippe@linaro.org> Cc: fenghua.yu@intel.com, catalin.marinas@arm.com, robin.murphy@arm.com, hch@infradead.org, zhengxiang9@huawei.com, zhangfei.gao@linaro.org, will@kernel.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Will, On Thu, Jun 18, 2020 at 05:51:13PM +0200, Jean-Philippe Brucker wrote: > Since v7 [1], I split the series into three parts to ease review. This > first one adds page table sharing to the SMMUv3 driver. The second one > adds support for I/O page faults through PRI and Stall, and the last one > adds additional and optional features (DVM, VHE and HTTU). SVA needs the > three parts to work. No significant change apart from that, I just > addressed the previous comments. > > I'd rather everything went through the IOMMU tree but I'm assuming patch > 1 will also go through the x86 tree as part of [2]. It is definitely > required by patch 3 which is required by patch 11. I don't know how this > kind of conflict is usually resolved, but if it's a problem I could > further shrink the series to only patches 4-10 this cycle. I have one bugfix for this series but am planning to hold off resending until you've found time to have a look. I can also reduce it to 7 patches for v4.9, please let me know what you prefer. Thanks, Jean > > [1] https://lore.kernel.org/linux-iommu/20200519175502.2504091-1-jean-philippe@linaro.org/ > [2] https://lore.kernel.org/linux-iommu/1592418233-17762-1-git-send-email-fenghua.yu@intel.com/ > > Fenghua Yu (1): > mm: Define pasid in mm > > Jean-Philippe Brucker (11): > iommu/ioasid: Add ioasid references > iommu/sva: Add PASID helpers > arm64: mm: Pin down ASIDs for sharing mm with devices > iommu/io-pgtable-arm: Move some definitions to a header > arm64: cpufeature: Export symbol read_sanitised_ftr_reg() > iommu/arm-smmu-v3: Share process page tables > iommu/arm-smmu-v3: Seize private ASID > iommu/arm-smmu-v3: Check for SVA features > iommu/arm-smmu-v3: Add SVA device feature > iommu/arm-smmu-v3: Implement iommu_sva_bind/unbind() > iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops > > drivers/iommu/Kconfig | 7 + > drivers/iommu/Makefile | 1 + > arch/arm64/include/asm/mmu.h | 1 + > arch/arm64/include/asm/mmu_context.h | 11 +- > drivers/iommu/io-pgtable-arm.h | 30 ++ > drivers/iommu/iommu-sva-lib.h | 15 + > include/linux/ioasid.h | 10 +- > include/linux/mm_types.h | 4 + > arch/arm64/kernel/cpufeature.c | 1 + > arch/arm64/mm/context.c | 95 +++- > drivers/iommu/arm-smmu-v3.c | 702 ++++++++++++++++++++++++++- > drivers/iommu/intel/iommu.c | 4 +- > drivers/iommu/intel/svm.c | 6 +- > drivers/iommu/io-pgtable-arm.c | 27 +- > drivers/iommu/ioasid.c | 38 +- > drivers/iommu/iommu-sva-lib.c | 85 ++++ > MAINTAINERS | 3 +- > 17 files changed, 977 insertions(+), 63 deletions(-) > create mode 100644 drivers/iommu/io-pgtable-arm.h > create mode 100644 drivers/iommu/iommu-sva-lib.h > create mode 100644 drivers/iommu/iommu-sva-lib.c > > -- > 2.27.0 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu