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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	 Rob Herring <robh+dt@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
	chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
	Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org, ming-fan.chen@mediatek.com,
	anan.sun@mediatek.com, Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 16/21] iommu/mediatek: Support up to 34bit iova in tlb invalid
Date: Sat, 11 Jul 2020 14:48:41 +0800	[thread overview]
Message-ID: <20200711064846.16007-17-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200711064846.16007-1-yong.wu@mediatek.com>

If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.

there is a minor change unrelated with this patch. it also use the new
macro.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 3b2714bea45a..9c6649a97bd7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -123,6 +123,8 @@ struct mtk_iommu_domain {
 
 static const struct iommu_ops mtk_iommu_ops;
 
+#define MTK_IOMMU_ADDR(addr)   (lower_32_bits(addr) | upper_32_bits(addr))
+
 /*
  * In M4U 4GB mode, the physical address is remapped as below:
  *
@@ -225,8 +227,9 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 		writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 			       data->base + data->plat_data->inv_sel_reg);
 
-		writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
-		writel_relaxed(iova + size - 1,
+		writel_relaxed(MTK_IOMMU_ADDR(iova),
+			       data->base + REG_MMU_INVLD_START_A);
+		writel_relaxed(MTK_IOMMU_ADDR(iova + size - 1),
 			       data->base + REG_MMU_INVLD_END_A);
 		writel_relaxed(F_MMU_INV_RANGE,
 			       data->base + REG_MMU_INVALIDATE);
@@ -653,8 +656,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 	if (data->plat_data->m4u_plat == M4U_MT8173)
 		regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
 	else
-		regval = lower_32_bits(data->protect_base) |
-			 upper_32_bits(data->protect_base);
+		regval = MTK_IOMMU_ADDR(data->protect_base);
 	writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
 
 	if (data->enable_4GB &&
-- 
2.18.0
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  parent reply	other threads:[~2020-07-11  6:52 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-11  6:48 [PATCH 00/21] MT8192 IOMMU support Yong Wu
2020-07-11  6:48 ` [PATCH 01/21] dt-binding: memory: mediatek: Add a common larb-port header file Yong Wu
2020-07-12 18:06   ` Matthias Brugger
2020-07-13  5:43     ` Pi-Hsun Shih
2020-07-13  6:28       ` Yong Wu
2020-07-13  6:27     ` [SPAM]Re: " Yong Wu
2020-07-20 22:58   ` Rob Herring
2020-07-11  6:48 ` [PATCH 02/21] dt-binding: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
2020-07-20 22:59   ` Rob Herring
2020-07-11  6:48 ` [PATCH 03/21] dt-binding: memory: mediatek: Add domain definition Yong Wu
2020-07-11  6:48 ` [PATCH 04/21] dt-binding: mediatek: Add binding for mt8192 IOMMU and SMI Yong Wu
2020-07-13  5:36   ` Pi-Hsun Shih
2020-07-13  6:54     ` Yong Wu
2020-07-20 23:16   ` Rob Herring
2020-07-21  3:27     ` Yong Wu
2020-07-11  6:48 ` [PATCH 05/21] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
2020-07-11  6:48 ` [PATCH 06/21] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
2020-07-13  0:38   ` Nicolas Boichat
2020-07-13  6:52     ` Yong Wu
2020-07-11  6:48 ` [PATCH 07/21] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
2020-07-11  6:48 ` [PATCH 08/21] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
2020-07-11  6:48 ` [PATCH 09/21] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
2020-07-11  6:48 ` [PATCH 10/21] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
2020-07-11  6:48 ` [PATCH 11/21] iommu/mediatek: Add power-domain operation Yong Wu
2020-07-13  7:03   ` Pi-Hsun Shih
2020-07-14  9:33     ` Yong Wu
2020-07-27  8:49   ` chao hao
2020-08-07  2:13     ` Yong Wu
2020-07-11  6:48 ` [PATCH 12/21] iommu/mediatek: Add iova reserved function Yong Wu
2020-07-13  7:33   ` Pi-Hsun Shih
2020-07-14  9:32     ` Yong Wu
2020-07-11  6:48 ` [PATCH 13/21] iommu/mediatek: Make MTK_IOMMU depend on ARM64 Yong Wu
2020-07-11  6:48 ` [PATCH 14/21] iommu/mediatek: Add single domain Yong Wu
2020-07-11  6:48 ` [PATCH 15/21] iommu/mediatek: Support master use iova over 32bit Yong Wu
2020-07-11  6:48 ` Yong Wu [this message]
2020-07-11  6:48 ` [PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
2020-07-11  6:48 ` [PATCH 18/21] iommu/mediatek: Add support for multi domain Yong Wu
2020-07-23 20:47   ` Rob Herring
2020-07-27  6:41     ` Yong Wu
2020-07-11  6:48 ` [PATCH 19/21] iommu/mediatek: Adjust the structure Yong Wu
2020-07-11  6:48 ` [PATCH 20/21] iommu/mediatek: Add mt8192 support Yong Wu
2020-07-11  6:48 ` [PATCH 21/21] memory: mtk-smi: " Yong Wu

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