From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Dimitri Sivanich <sivanich@hpe.com>,
linux-hyperv@vger.kernel.org, Steve Wahl <steve.wahl@hpe.com>,
linux-pci@vger.kernel.org, "K. Y. Srinivasan" <kys@microsoft.com>,
Dan Williams <dan.j.williams@intel.com>,
Wei Liu <wei.liu@kernel.org>,
Stephen Hemminger <sthemmin@microsoft.com>,
Baolu Lu <baolu.lu@intel.com>, Marc Zyngier <maz@kernel.org>,
x86@kernel.org, Jason Gunthorpe <jgg@mellanox.com>,
Megha Dey <megha.dey@intel.com>,
xen-devel@lists.xenproject.org, Kevin Tian <kevin.tian@intel.com>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Haiyang Zhang <haiyangz@microsoft.com>,
Alex Williamson <alex.williamson@redhat.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Jonathan Derrick <jonathan.derrick@intel.com>,
Juergen Gross <jgross@suse.com>, Russ Anderson <rja@hpe.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
iommu@lists.linux-foundation.org,
Jacob Pan <jacob.jun.pan@intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>
Subject: [patch RFC 12/38] x86/irq: Consolidate UV domain allocation
Date: Fri, 21 Aug 2020 02:24:36 +0200 [thread overview]
Message-ID: <20200821002946.500438544@linutronix.de> (raw)
In-Reply-To: 20200821002424.119492231@linutronix.de
[-- Attachment #1: x86-irq--Consolidate-UV-domain-allocation.patch --]
[-- Type: text/plain, Size: 2974 bytes --]
Move the UV specific fields into their own struct for readability sake. Get
rid of the #ifdeffery as it does not matter at all whether the alloc info
is a couple of bytes longer or not.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Steve Wahl <steve.wahl@hpe.com>
Cc: Dimitri Sivanich <sivanich@hpe.com>
Cc: Russ Anderson <rja@hpe.com>
---
arch/x86/include/asm/hw_irq.h | 21 ++++++++++++---------
arch/x86/platform/uv/uv_irq.c | 16 ++++++++--------
2 files changed, 20 insertions(+), 17 deletions(-)
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -53,6 +53,14 @@ struct ioapic_alloc_info {
struct IO_APIC_route_entry *entry;
};
+struct uv_alloc_info {
+ int limit;
+ int blade;
+ unsigned long offset;
+ char *name;
+
+};
+
/**
* irq_alloc_info - X86 specific interrupt allocation info
* @type: X86 specific allocation type
@@ -64,7 +72,8 @@ struct ioapic_alloc_info {
* @data: Allocation specific data
*
* @ioapic: IOAPIC specific allocation data
- */
+ * @uv: UV specific allocation data
+*/
struct irq_alloc_info {
enum irq_alloc_type type;
u32 flags;
@@ -76,6 +85,8 @@ struct irq_alloc_info {
union {
struct ioapic_alloc_info ioapic;
+ struct uv_alloc_info uv;
+
int unused;
#ifdef CONFIG_PCI_MSI
struct {
@@ -83,14 +94,6 @@ struct irq_alloc_info {
irq_hw_number_t msi_hwirq;
};
#endif
-#ifdef CONFIG_X86_UV
- struct {
- int uv_limit;
- int uv_blade;
- unsigned long uv_offset;
- char *uv_name;
- };
-#endif
};
};
--- a/arch/x86/platform/uv/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
@@ -90,15 +90,15 @@ static int uv_domain_alloc(struct irq_do
ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
if (ret >= 0) {
- if (info->uv_limit == UV_AFFINITY_CPU)
+ if (info->uv.limit == UV_AFFINITY_CPU)
irq_set_status_flags(virq, IRQ_NO_BALANCING);
else
irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
- chip_data->pnode = uv_blade_to_pnode(info->uv_blade);
- chip_data->offset = info->uv_offset;
+ chip_data->pnode = uv_blade_to_pnode(info->uv.blade);
+ chip_data->offset = info->uv.offset;
irq_domain_set_info(domain, virq, virq, &uv_irq_chip, chip_data,
- handle_percpu_irq, NULL, info->uv_name);
+ handle_percpu_irq, NULL, info->uv.name);
} else {
kfree(chip_data);
}
@@ -193,10 +193,10 @@ int uv_setup_irq(char *irq_name, int cpu
init_irq_alloc_info(&info, cpumask_of(cpu));
info.type = X86_IRQ_ALLOC_TYPE_UV;
- info.uv_limit = limit;
- info.uv_blade = mmr_blade;
- info.uv_offset = mmr_offset;
- info.uv_name = irq_name;
+ info.uv.limit = limit;
+ info.uv.blade = mmr_blade;
+ info.uv.offset = mmr_offset;
+ info.uv.name = irq_name;
return irq_domain_alloc_irqs(domain, 1,
uv_blade_to_memory_nid(mmr_blade), &info);
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-08-21 2:17 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-21 0:24 [patch RFC 00/38] x86, PCI, XEN, genirq ...: Prepare for device MSI Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 01/38] iommu/amd: Prevent NULL pointer dereference Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 02/38] x86/init: Remove unused init ops Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 03/38] x86/irq: Rename X86_IRQ_ALLOC_TYPE_MSI* to reflect PCI dependency Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 04/38] x86/irq: Add allocation type for parent domain retrieval Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 05/38] iommu/vt-d: Consolidate irq domain getter Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 06/38] iommu/amd: " Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 07/38] iommu/irq_remapping: Consolidate irq domain lookup Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 08/38] x86/irq: Prepare consolidation of irq_alloc_info Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 09/38] x86/msi: Consolidate HPET allocation Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 10/38] x86/ioapic: Consolidate IOAPIC allocation Thomas Gleixner
2020-08-26 8:40 ` Boqun Feng
2020-08-26 9:53 ` Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 11/38] x86/irq: Consolidate DMAR irq allocation Thomas Gleixner
2020-08-21 0:24 ` Thomas Gleixner [this message]
2020-08-21 0:24 ` [patch RFC 13/38] PCI: MSI: Rework pci_msi_domain_calc_hwirq() Thomas Gleixner
2020-08-25 20:03 ` Bjorn Helgaas
2020-08-25 21:11 ` Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 14/38] x86/msi: Consolidate MSI allocation Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 15/38] x86/msi: Use generic MSI domain ops Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 16/38] x86/irq: Move apic_post_init() invocation to one place Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 17/38] x86/pci: Reducde #ifdeffery in PCI init code Thomas Gleixner
2020-08-25 20:20 ` Bjorn Helgaas
2020-08-21 0:24 ` [patch RFC 18/38] x86/irq: Initialize PCI/MSI domain at PCI init time Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 19/38] irqdomain/msi: Provide DOMAIN_BUS_VMD_MSI Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 20/38] PCI: vmd: Mark VMD irqdomain with DOMAIN_BUS_VMD_MSI Thomas Gleixner
2020-08-25 20:04 ` Bjorn Helgaas
2020-08-21 0:24 ` [patch RFC 21/38] PCI: MSI: Provide pci_dev_has_special_msi_domain() helper Thomas Gleixner
2020-08-25 20:16 ` Bjorn Helgaas
2020-08-21 0:24 ` [patch RFC 22/38] x86/xen: Make xen_msi_init() static and rename it to xen_hvm_msi_init() Thomas Gleixner
2020-08-24 4:48 ` Jürgen Groß
2020-08-21 0:24 ` [patch RFC 23/38] x86/xen: Rework MSI teardown Thomas Gleixner
2020-08-24 5:09 ` Jürgen Groß
2020-08-21 0:24 ` [patch RFC 24/38] x86/xen: Consolidate XEN-MSI init Thomas Gleixner
2020-08-24 4:59 ` Jürgen Groß
2020-08-24 21:21 ` Thomas Gleixner
2020-08-25 4:21 ` Jürgen Groß
2020-08-25 9:51 ` Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 25/38] irqdomain/msi: Allow to override msi_domain_alloc/free_irqs() Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 26/38] x86/xen: Wrap XEN MSI management into irqdomain Thomas Gleixner
2020-08-24 6:21 ` Jürgen Groß
2020-08-25 7:57 ` Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 27/38] iommm/vt-d: Store irq domain in struct device Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 28/38] iommm/amd: " Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 29/38] x86/pci: Set default irq domain in pcibios_add_device() Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 30/38] PCI/MSI: Allow to disable arch fallbacks Thomas Gleixner
2020-08-25 20:07 ` Bjorn Helgaas
2020-08-25 21:28 ` Thomas Gleixner
2020-08-25 21:35 ` Bjorn Helgaas
2020-08-25 21:40 ` Thomas Gleixner
2020-08-25 22:03 ` Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 31/38] x86/irq: Cleanup the arch_*_msi_irqs() leftovers Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 32/38] x86/irq: Make most MSI ops XEN private Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 33/38] x86/irq: Add DEV_MSI allocation type Thomas Gleixner
2020-08-21 0:24 ` [patch RFC 34/38] x86/msi: Let pci_msi_prepare() handle non-PCI MSI Thomas Gleixner
2020-08-25 20:24 ` Bjorn Helgaas
2020-08-25 21:30 ` Thomas Gleixner
2020-08-25 21:50 ` Bjorn Helgaas
2020-08-21 0:24 ` [patch RFC 35/38] platform-msi: Provide default irq_chip::ack Thomas Gleixner
2020-08-21 0:25 ` [patch RFC 36/38] platform-msi: Add device MSI infrastructure Thomas Gleixner
2020-08-21 0:25 ` [patch RFC 37/38] irqdomain/msi: Provide msi_alloc/free_store() callbacks Thomas Gleixner
2020-08-21 0:25 ` [patch RFC 38/38] irqchip: Add IMS array driver - NOT FOR MERGING Thomas Gleixner
2020-08-21 12:45 ` Jason Gunthorpe
2020-08-21 19:47 ` Thomas Gleixner
2020-08-21 20:17 ` Jason Gunthorpe
2020-08-21 23:47 ` Thomas Gleixner
2020-08-22 0:51 ` Jason Gunthorpe
2020-08-22 1:34 ` Thomas Gleixner
2020-08-22 23:05 ` Jason Gunthorpe
2020-08-23 8:03 ` Thomas Gleixner
2020-08-22 14:19 ` [patch RFC 00/38] x86, PCI, XEN, genirq ...: Prepare for device MSI Jürgen Groß
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200821002946.500438544@linutronix.de \
--to=tglx@linutronix.de \
--cc=alex.williamson@redhat.com \
--cc=baolu.lu@intel.com \
--cc=bhelgaas@google.com \
--cc=boris.ostrovsky@oracle.com \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=haiyangz@microsoft.com \
--cc=iommu@lists.linux-foundation.org \
--cc=jacob.jun.pan@intel.com \
--cc=jgg@mellanox.com \
--cc=jgross@suse.com \
--cc=jonathan.derrick@intel.com \
--cc=kevin.tian@intel.com \
--cc=konrad.wilk@oracle.com \
--cc=kys@microsoft.com \
--cc=linux-hyperv@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=maz@kernel.org \
--cc=megha.dey@intel.com \
--cc=rafael@kernel.org \
--cc=rja@hpe.com \
--cc=sivanich@hpe.com \
--cc=sstabellini@kernel.org \
--cc=steve.wahl@hpe.com \
--cc=sthemmin@microsoft.com \
--cc=wei.liu@kernel.org \
--cc=x86@kernel.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).