From: Steven Price <steven.price@arm.com>
To: Robin Murphy <robin.murphy@arm.com>, will@kernel.org, joro@8bytes.org
Cc: robh@kernel.org, iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org, tomeu.vizoso@collabora.com,
narmstrong@baylibre.com
Subject: Re: [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali
Date: Thu, 12 Sep 2019 11:53:52 +0100 [thread overview]
Message-ID: <5aee1c30-65ba-a608-6033-dedf004b24ea@arm.com> (raw)
In-Reply-To: <8eb563978e7e872ddde45c0413e1a3f30b792658.1568211045.git.robin.murphy@arm.com>
On 11/09/2019 15:42, Robin Murphy wrote:
> Midgard GPUs have ACE-Lite master interfaces which allows systems to
> integrate them in an I/O-coherent manner. It seems that from the GPU's
> viewpoint, the rest of the system is its outer shareable domain, and it
> will only emit snoop signals for outer shareable accesses. As such,
> setting the TTBR_SHARE_OUTER bit does indeed get coherent pagetable
> walks working nicely.
>
> Making data accesses coherent seems to be more of a challenge...
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Note the terminology in the GPU is *very* confusing here. Midgard refers
to the system's inner shareable domain as "outer shareable", and uses
"inner shareable" to mean purely within the GPU.
For data access kbase sets up a different default MEMATTR if ACE is
available:
/* Set to implementation defined, outer caching */
#define AS_MEMATTR_LPAE_OUTER_IMPL_DEF 0x88ull
[...]
#define AS_MEMATTR_INDEX_DEFAULT_ACE 3
[...]
/* Outer coherent, inner implementation defined policy */
#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3
Steve
> ---
> drivers/iommu/io-pgtable-arm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 77f41c9dd9be..2794d4661339 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1061,6 +1061,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
> cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
> ARM_MALI_LPAE_TTBR_READ_INNER |
> ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
> + if (cfg->coherent_walk)
> + cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
> +
> return &data->iop;
>
> out_free_data:
>
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next prev parent reply other threads:[~2019-09-12 10:53 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
2019-09-12 10:41 ` Steven Price
2019-09-11 14:42 ` [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations Robin Murphy
2019-09-12 10:47 ` Steven Price
2019-09-11 14:42 ` [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
2019-09-12 10:53 ` Steven Price [this message]
2019-09-11 16:19 ` [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Neil Armstrong
2019-09-11 16:20 ` Will Deacon
2019-09-11 17:19 ` Robin Murphy
2019-09-19 8:30 ` Will Deacon
2019-09-23 8:17 ` Tomeu Vizoso
2019-09-23 11:04 ` Robin Murphy
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