From: Rob Clark <robdclark@gmail.com>
To: Jordan Crouse <jcrouse@codeaurora.org>
Cc: freedreno <freedreno@lists.freedesktop.org>,
David Airlie <airlied@linux.ie>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>,
Joerg Roedel <joro@8bytes.org>,
" <iommu@lists.linux-foundation.org>,
Mamta Shukla <mamtashukla555@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
Sean Paul <sean@poorly.run>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 7/8] drm/msm/a6xx: Support split pagetables
Date: Mon, 9 Dec 2019 12:17:53 -0800 [thread overview]
Message-ID: <CAF6AEGuchn7fa+8j45sCH7Sd2_dz5WokeeinR8RYr8xvY4Uq+g@mail.gmail.com> (raw)
In-Reply-To: <0101016e95754ea7-d6414f4c-9e25-4bc4-a852-7116a783bf63-000000@us-west-2.amazonses.com>
On Fri, Nov 22, 2019 at 3:32 PM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Attempt to enable split pagetables if the arm-smmu driver supports it.
> This will move the default address space from the default region to
> the address range assigned to TTBR1. The behavior should be transparent
> to the driver for now but it gets the default buffers out of the way
> when we want to start swapping TTBR0 for context-specific pagetables.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 5dc0b2c..96b3b28 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -811,6 +811,50 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
> return (unsigned long)busy_time;
> }
>
> +static struct msm_gem_address_space *
> +a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
> +{
> + struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
> + struct msm_gem_address_space *aspace;
> + struct msm_mmu *mmu;
> + u64 start, size;
> + u32 val = 1;
> + int ret;
> +
> + if (!iommu)
> + return ERR_PTR(-ENOMEM);
> +
> + /* Try to request split pagetables */
> + iommu_domain_set_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val);
> +
> + mmu = msm_iommu_new(&pdev->dev, iommu);
> + if (IS_ERR(mmu)) {
> + iommu_domain_free(iommu);
> + return ERR_CAST(mmu);
> + }
> +
> + /* Check to see if split pagetables were successful */
> + ret = iommu_domain_get_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val);
I assume the split between this and iommu_domain_set_attr() is because
attach needs to happen in between? At any rate, if it needs to be
like this, maybe a comment is in order. As it is it looks like
something future-self would "cleanup"..
BR,
-R
> + if (!ret && val) {
> + /*
> + * The aperture start will be at the beginning of the TTBR1
> + * space so use that as a base
> + */
> + start = iommu->geometry.aperture_start;
> + size = 0xffffffff;
> + } else {
> + /* Otherwise use the legacy 32 bit region */
> + start = SZ_16M;
> + size = 0xffffffff - SZ_16M;
> + }
> +
> + aspace = msm_gem_address_space_create(mmu, "gpu", start, size);
> + if (IS_ERR(aspace))
> + iommu_domain_free(iommu);
> +
> + return aspace;
> +}
> +
> static const struct adreno_gpu_funcs funcs = {
> .base = {
> .get_param = adreno_get_param,
> @@ -832,7 +876,7 @@ static const struct adreno_gpu_funcs funcs = {
> #if defined(CONFIG_DRM_MSM_GPU_STATE)
> .gpu_state_get = a6xx_gpu_state_get,
> .gpu_state_put = a6xx_gpu_state_put,
> - .create_address_space = adreno_iommu_create_address_space,
> + .create_address_space = a6xx_create_address_space,
> #endif
> },
> .get_timestamp = a6xx_get_timestamp,
> --
> 2.7.4
>
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prev parent reply other threads:[~2019-12-09 20:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1574465484-7115-1-git-send-email-jcrouse@codeaurora.org>
2019-11-22 23:31 ` [PATCH v2 1/8] dt-bindings: arm-smmu: Add Adreno GPU variant Jordan Crouse
2019-11-22 23:31 ` [PATCH v2 2/8] iommu: Add DOMAIN_ATTR_SPLIT_TABLES Jordan Crouse
2019-11-22 23:31 ` [PATCH v2 3/8] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context Jordan Crouse
2019-11-22 23:31 ` [PATCH v2 4/8] iommu/arm-smmu: Add split pagetables for Adreno IOMMU implementations Jordan Crouse
2019-11-22 23:31 ` [PATCH v2 5/8] drm/msm: Attach the IOMMU device during initialization Jordan Crouse
2019-11-22 23:32 ` [PATCH v2 7/8] drm/msm/a6xx: Support split pagetables Jordan Crouse
2019-11-22 23:32 ` [PATCH v2 8/8] arm64: dts: qcom: sdm845: Update Adreno GPU SMMU compatible string Jordan Crouse
2019-11-22 23:32 ` [PATCH v2 6/8] drm/msm: Refactor address space initialization Jordan Crouse
[not found] ` <0101016e95751ea5-da4da251-ddba-4017-9258-b2cfd4e06f7f-000000@us-west-2.amazonses.com>
2019-12-03 19:14 ` [PATCH v2 1/8] dt-bindings: arm-smmu: Add Adreno GPU variant Rob Herring
[not found] ` <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com>
2019-12-04 15:55 ` Robin Murphy
2019-12-04 18:01 ` Rob Clark
[not found] ` <0101016e95752703-78491f46-41db-441c-b0fb-9a760e4d56cb-000000@us-west-2.amazonses.com>
2019-12-04 16:44 ` [PATCH v2 4/8] iommu/arm-smmu: Add split pagetables for Adreno IOMMU implementations Robin Murphy
2019-12-05 15:51 ` Jordan Crouse
[not found] ` <0101016e95754002-c2fa43aa-b14b-4cff-b6f9-a67c96661e26-000000@us-west-2.amazonses.com>
2019-12-09 20:11 ` [PATCH v2 5/8] drm/msm: Attach the IOMMU device during initialization Rob Clark
[not found] ` <0101016e95755c16-5ab6f6e7-83bb-4d01-b746-7cc6ea265ad7-000000@us-west-2.amazonses.com>
2019-12-09 20:14 ` [PATCH v2 6/8] drm/msm: Refactor address space initialization Rob Clark
[not found] ` <0101016e95754ea7-d6414f4c-9e25-4bc4-a852-7116a783bf63-000000@us-west-2.amazonses.com>
2019-12-09 20:17 ` Rob Clark [this message]
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