From: Saheed Olayemi Bolarinwa <refactormyself@gmail.com>
To: helgaas@kernel.org
Cc: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel-mentees@lists.linuxfoundation.org
Subject: [Linux-kernel-mentees] [PATCH 12/13] PCI/ASPM: Check the return value of pcie_capability_read_*()
Date: Wed, 8 Jul 2020 00:03:23 +0200 [thread overview]
Message-ID: <20200707220324.8425-13-refactormyself@gmail.com> (raw)
In-Reply-To: <20200707220324.8425-1-refactormyself@gmail.com>
From: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>
On failure pcie_capability_read_dword() sets it's last parameter,
val to 0.
However, with Patch 13/13, it is possible that val is set to ~0 on
failure. This would introduce a bug because (x & x) == (~0 & x).
This bug can be avoided if the return value of pcie_capability_read_dword
is checked to confirm success.
Check the return value of pcie_capability_read_dword() to ensure success.
Suggested-by: Bjorn Helgaas <bjorn@helgaas.com>
Signed-off-by: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>
---
drivers/pci/pcie/aspm.c | 33 +++++++++++++++++----------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index b17e5ffd31b1..32aa9d57672a 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -176,7 +176,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
{
- int capable = 1, enabled = 1;
+ int ret, capable = 1, enabled = 1;
u32 reg32;
u16 reg16;
struct pci_dev *child;
@@ -184,14 +184,14 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
/* All functions should have the same cap and state, take the worst */
list_for_each_entry(child, &linkbus->devices, bus_list) {
- pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
- if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
+ ret = pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
+ if (ret || !(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
capable = 0;
enabled = 0;
break;
}
- pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
- if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
+ ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
+ if (ret || !(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
enabled = 0;
}
link->clkpm_enabled = enabled;
@@ -205,6 +205,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link)
struct pci_dev *parent = link->pdev;
unsigned long end_jiffies;
u16 reg16;
+ int ret;
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
reg16 |= PCI_EXP_LNKCTL_RL;
@@ -222,8 +223,8 @@ static bool pcie_retrain_link(struct pcie_link_state *link)
/* Wait for link training end. Break out after waiting for timeout */
end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
do {
- pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_LT))
+ ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
+ if (ret || !(reg16 & PCI_EXP_LNKSTA_LT))
break;
msleep(1);
} while (time_before(jiffies, end_jiffies));
@@ -237,7 +238,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link)
*/
static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
{
- int same_clock = 1;
+ int ret, same_clock = 1;
u16 reg16, parent_reg, child_reg[8];
struct pci_dev *child, *parent = link->pdev;
struct pci_bus *linkbus = parent->subordinate;
@@ -249,24 +250,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
BUG_ON(!pci_is_pcie(child));
/* Check downstream component if bit Slot Clock Configuration is 1 */
- pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_SLC))
+ ret = pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
+ if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC))
same_clock = 0;
/* Check upstream component if bit Slot Clock Configuration is 1 */
- pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
- if (!(reg16 & PCI_EXP_LNKSTA_SLC))
+ ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
+ if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC))
same_clock = 0;
/* Port might be already in common clock mode */
- pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
- if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
+ ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
+ if (!ret && same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
bool consistent = true;
list_for_each_entry(child, &linkbus->devices, bus_list) {
- pcie_capability_read_word(child, PCI_EXP_LNKCTL,
+ ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL,
®16);
- if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
+ if (ret || !(reg16 & PCI_EXP_LNKCTL_CCC)) {
consistent = false;
break;
}
--
2.18.2
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next prev parent reply other threads:[~2020-07-07 23:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-07 22:03 [Linux-kernel-mentees] [PATCH 0/13] PCI: Remove '*val = 0' from pcie_capability_read_*() Saheed Olayemi Bolarinwa
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 2/13] misc: rtsx: Check the return value of pcie_capability_read_*() Saheed Olayemi Bolarinwa
2020-07-08 6:53 ` Greg Kroah-Hartman
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 5/13] PCI: pciehp: " Saheed Olayemi Bolarinwa
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 6/13] PCI: pciehp: Make "Power On" the default Saheed Olayemi Bolarinwa
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 8/13] PCI: pciehp: Check return value of pcie_capability_read_*() Saheed Olayemi Bolarinwa
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 9/13] PCI: " Saheed Olayemi Bolarinwa
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 10/13] PCI/PM: " Saheed Olayemi Bolarinwa
2020-07-07 22:03 ` Saheed Olayemi Bolarinwa [this message]
2020-07-07 22:03 ` [Linux-kernel-mentees] [PATCH 13/13] PCI: Remove '*val = 0' from pcie_capability_read_*() Saheed Olayemi Bolarinwa
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