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From: Jan Kotas <jank@cadence.com>
To: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Jan Kotas <jank@cadence.com>,
	Maxime Ripard <maxime.ripard@bootlin.com>,
	"mchehab@kernel.org" <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Rafal Ciepiela <rafalc@cadence.com>,
	linux-media <linux-media@vger.kernel.org>,
	linux-devicetree <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/3] media: Add lane checks for Cadence CSI2RX
Date: Mon, 9 Sep 2019 08:12:54 +0000	[thread overview]
Message-ID: <6F0DAE9B-BD7F-44D6-8D5B-92B3B3099CF2@global.cadence.com> (raw)
In-Reply-To: <20190909075153.GA843@valkosipuli.retiisi.org.uk>



> On 9 Sep 2019, at 09:51, Sakari Ailus <sakari.ailus@iki.fi> wrote:
> 
> 
> On Mon, Sep 09, 2019 at 07:41:21AM +0000, Jan Kotas wrote:
>> 
>> 
>> Hello Sakari,
>> 
>> Thanks for your reply.
>>> On 6 Sep 2019, at 09:54, Sakari Ailus <sakari.ailus@iki.fi> wrote:
>>> 
>>> Hi Jan,
>>> 
>>> Thanks for the patchset.
>>> 
>>> On Thu, Sep 05, 2019 at 11:56:00AM +0100, Jan Kotas wrote:
>>>> /*
>>>> * Driver for Cadence MIPI-CSI2 RX Controller v1.3
>>>> *
>>>> - * Copyright (C) 2017 Cadence Design Systems Inc.
>>>> + * Copyright (C) 2017-2019 Cadence Design Systems Inc.
>>>> */
>>>> 
>>>> +	for (i = 0; i < csi2rx->num_lanes; i++) {
>>>> +		if (csi2rx->lanes[i] < 1) {
>>> 
>>> Do you need this? v4l2_fwnode_parse_endpoint() already has a more thorough
>>> check for the lane numbers.
>> 
>> I looked at the source code of v4l2_fwnode_endpoint_parse_csi2_bus
>> and this particular case doesn’t seem to be checked.
> 
> Not specifically, since 0 is a valid lane number.
> 
> However, the driver only appears to be using the information on how many
> lanes there are. If the hardware doesn't support lane routing, then this is
> all you need. Otherwise additional checks should be added in case there are
> limitations how the lanes can be routed.

The CSI2RX v1.3 does support that (CSI2RX_STATIC_CFG_REG)
and assumes the first data lane has number 1.

Regrads,
Jan

> -- 
> Sakari Ailus


  reply	other threads:[~2019-09-09  8:13 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-05 10:55 [PATCH v2 0/3] media: Add support for Cadence CSI2RX version 2.1 Jan Kotas
2019-09-05 10:55 ` [PATCH v2 1/3] media: dt-bindings: Update bindings for Cadence CSI2RX Jan Kotas
2019-09-17 20:52   ` Rob Herring
2019-09-05 10:56 ` [PATCH v2 2/3] media: Add lane checks " Jan Kotas
2019-09-06  7:54   ` Sakari Ailus
2019-09-09  7:41     ` Jan Kotas
2019-09-09  7:51       ` Sakari Ailus
2019-09-09  8:12         ` Jan Kotas [this message]
2019-09-09  9:40           ` Sakari Ailus
2019-09-05 10:56 ` [PATCH v2 3/3] media: Add support for Cadence CSI2RX 2.1 Jan Kotas
2019-09-06  8:01   ` Sakari Ailus
2019-09-09  9:24     ` Jan Kotas
2019-09-09  9:41       ` Sakari Ailus
2019-09-05 12:01 ` [PATCH v2 0/3] media: Add support for Cadence CSI2RX version 2.1 Maxime Ripard

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