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From: Vishal Sagar <vsagar@xilinx.com>
To: Luca Ceresoli <luca@lucaceresoli.net>,
	Vishal Sagar <vishal.sagar@xilinx.com>,
	Hyun Kwon <hyunk@xilinx.com>,
	"laurent.pinchart@ideasonboard.com" 
	<laurent.pinchart@ideasonboard.com>,
	"mchehab@kernel.org" <mchehab@kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	Michal Simek <michals@xilinx.com>,
	"linux-media@vger.kernel.org" <linux-media@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"sakari.ailus@linux.intel.com" <sakari.ailus@linux.intel.com>,
	"hans.verkuil@cisco.com" <hans.verkuil@cisco.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Dinesh Kumar <dineshk@xilinx.com>,
	Sandip Kothari <sandipk@xilinx.com>
Subject: RE: [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
Date: Tue, 12 Mar 2019 04:36:28 +0000	[thread overview]
Message-ID: <CY4PR02MB2709BECF081E32B5D4EA5354A7490@CY4PR02MB2709.namprd02.prod.outlook.com> (raw)
In-Reply-To: <1f698576-89b2-e264-387e-6db4c5a4713a@lucaceresoli.net>

Hi Luca,

> -----Original Message-----
> From: Luca Ceresoli [mailto:luca@lucaceresoli.net]
> Sent: Monday, March 11, 2019 5:38 PM
> To: Vishal Sagar <vsagar@xilinx.com>; Vishal Sagar <vishal.sagar@xilinx.com>;
> Hyun Kwon <hyunk@xilinx.com>; laurent.pinchart@ideasonboard.com;
> mchehab@kernel.org; robh+dt@kernel.org; mark.rutland@arm.com; Michal
> Simek <michals@xilinx.com>; linux-media@vger.kernel.org;
> devicetree@vger.kernel.org; sakari.ailus@linux.intel.com;
> hans.verkuil@cisco.com; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Dinesh Kumar <dineshk@xilinx.com>; Sandip Kothari
> <sandipk@xilinx.com>
> Subject: Re: [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> On 08/03/19 20:04, Vishal Sagar wrote:
> >>> +Optional properties:
> >>> +--------------------
> >>> +- xlnx,vfb: This is present when Video Format Bridge is enabled.
> >>> +  Without this property the driver won't be loaded as IP won't be able to
> >> generate
> >>> +  media bus format compliant stream output.
> >>> +- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
> >>> +- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
> >>> +  only 4. This is present only if xlnx,en-csi-v2-0 is present.
> >>> +- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol
> >>> +  Configuration Register.
> >>
> >> This doesn't seem very clear to me. According to my understanding of the
> >> IP and driver, I'd rather rephrase as:
> >>
> >> - xlnx,en-active-lanes: present if the number of active lanes can be
> >>   reconfigured at runtime in the Protocol Configuration Register.
> >>   If present, the V4L2_CID_XILINX_MIPICSISS_ACT_LANES is added.
> >>   Otherwise all lanes are always active.
> >>
> >
> > Your description is better. I will update with this in next version.
> 
> Ok, thanks. But I just noticed an error in my own words...
> "V4L2_CID_XILINX_MIPICSISS_ACT_LANES is added" ->
> "V4L2_CID_XILINX_MIPICSISS_ACT_LANES control is added".
> 
> --
> Luca

Ok I will do this in next round of patch.

Regards
Vishal Sagar

  reply	other threads:[~2019-03-12  4:36 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-01 12:56 [PATCH v3 0/2] Add support for Xilinx CSI2 Receiver Subsystem Vishal Sagar
2019-02-01 12:56 ` [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem Vishal Sagar
2019-02-11 10:42   ` Luca Ceresoli
2019-03-08 19:04     ` Vishal Sagar
2019-03-11 12:08       ` Luca Ceresoli
2019-03-12  4:36         ` Vishal Sagar [this message]
2019-02-01 12:56 ` [PATCH v3 2/2] media: v4l: " Vishal Sagar
2019-02-11 10:42   ` Luca Ceresoli
2019-02-11 12:43     ` Vishal Sagar
2019-02-11 14:30       ` Luca Ceresoli
2019-02-22 12:05         ` Vishal Sagar
2019-02-13 19:45   ` [v3,2/2] " Hyun Kwon
2019-02-22 12:06     ` Vishal Sagar

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