From: chao hao <Chao.Hao@mediatek.com>
To: Yong Wu <yong.wu@mediatek.com>
Cc: FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, Chao Hao <"chao hao"@mediatek.com>,
Joerg Roedel <joro@8bytes.org>,
iommu@lists.linux-foundation.org,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>
Subject: Re: [PATCH v5 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL
Date: Fri, 3 Jul 2020 10:36:24 +0800 [thread overview]
Message-ID: <1593743784.22738.0.camel@mbjsdccf07> (raw)
In-Reply-To: <1593569872.32037.6.camel@mhfsdcap03>
On Wed, 2020-07-01 at 10:17 +0800, Yong Wu wrote:
> On Mon, 2020-06-29 at 15:13 +0800, Chao Hao wrote:
> > For iommu offset=0x48 register, only the previous mt8173/mt8183 use the
> > name STANDARD_AXI_MODE, all the latest SoC extend the register more
> > feature by different bits, for example: axi_mode, in_order_en, coherent_en
> > and so on. So rename REG_MMU_MISC_CTRL may be more proper.
> >
> > This patch only rename the register name, no functional change.
> >
> > Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> > Reviewed-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> > drivers/iommu/mtk_iommu.c | 14 +++++++-------
> > drivers/iommu/mtk_iommu.h | 2 +-
> > 2 files changed, 8 insertions(+), 8 deletions(-)
>
> ...
>
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index ea949a324e33..1b6ea839b92c 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -18,7 +18,7 @@
> > #include <soc/mediatek/smi.h>
> >
> > struct mtk_iommu_suspend_reg {
> > - u32 standard_axi_mode;
> > + u32 misc_ctrl;
>
> Here will cause build fail for v1:
>
> drivers/iommu/mtk_iommu_v1.c:675:20: error: 'struct
> mtk_iommu_suspend_reg' has no member named 'standard_axi_mode'
> writel_relaxed(reg->standard_axi_mode,
> ^
>
> We could change something like:
>
> union {
> u32 standard_axi_mode; /* only for v1 */
> u32 misc_ctrl; /* only for v2 */
> };
>
> > u32 dcm_dis;
> > u32 ctrl_reg;
> > u32 int_control0;
ok, I will fix it in next version, thanks
>
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next prev parent reply other threads:[~2020-07-03 2:48 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 7:13 [PATCH v5 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-06-29 7:13 ` [PATCH v5 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-06-29 7:13 ` [PATCH v5 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-01 2:17 ` Yong Wu
2020-07-03 2:36 ` chao hao [this message]
2020-06-29 7:13 ` [PATCH v5 03/10] iommu/mediatek: Modify the usage of mtk_iommu_plat_data structure Chao Hao
2020-06-29 9:11 ` Matthias Brugger
2020-06-30 10:56 ` Yong Wu
2020-06-30 11:55 ` chao hao
2020-06-29 7:13 ` [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-06-29 9:28 ` Matthias Brugger
2020-06-30 10:53 ` chao hao
2020-07-01 14:58 ` Matthias Brugger
2020-07-03 2:38 ` chao hao
2020-06-29 7:13 ` [PATCH v5 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-06-29 7:13 ` [PATCH v5 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-06-30 10:55 ` Yong Wu
2020-06-30 11:07 ` chao hao
2020-06-29 7:13 ` [PATCH v5 07/10] iommu/mediatek: Add REG_MMU_WR_LEN register definition Chao Hao
2020-06-29 10:16 ` Matthias Brugger
2020-06-30 10:59 ` chao hao
2020-07-01 15:00 ` Matthias Brugger
2020-06-29 7:13 ` [PATCH v5 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-06-29 10:17 ` Matthias Brugger
2020-06-29 7:13 ` [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-06-29 10:28 ` Matthias Brugger
2020-06-30 11:02 ` chao hao
2020-06-29 7:13 ` [PATCH v5 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-06-29 10:29 ` Matthias Brugger
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