From: Roger Lu <roger.lu@mediatek.com>
To: Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
Angus Lin <Angus.Lin@mediatek.com>,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
Roger Lu <roger.lu@mediatek.com>,
linux-kernel@vger.kernel.org,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
YT Lee <yt.lee@mediatek.com>, Fan Chen <fan.chen@mediatek.com>,
linux-mediatek@lists.infradead.org,
HenryC Chen <HenryC.Chen@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 2/3] arm64: dts: mt8183: add svs device information
Date: Tue, 7 Jan 2020 15:01:53 +0800 [thread overview]
Message-ID: <20200107070154.1574-3-roger.lu@mediatek.com> (raw)
In-Reply-To: <20200107070154.1574-1-roger.lu@mediatek.com>
add pmic/clock/irq/efuse setting in svs node
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 16 ++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 41 +++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 1fb195c683c3..6ae1d9a1bcbf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -231,6 +231,22 @@
};
+&svs_cpu_little {
+ vcpu-little-supply = <&mt6358_vproc12_reg>;
+};
+
+&svs_cpu_big {
+ vcpu-big-supply = <&mt6358_vproc11_reg>;
+};
+
+&svs_cci {
+ vcci-supply = <&mt6358_vproc12_reg>;
+};
+
+&svs_gpu {
+ vgpu-spply = <&mt6358_vgpu_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 10b32471bc7b..996e65942f48 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -389,6 +389,39 @@
status = "disabled";
};
+ svs: svs@1100b000 {
+ compatible = "mediatek,mt8183-svs";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calibration>,
+ <&thermal_calibration>;
+ nvmem-cell-names = "svs-calibration-data",
+ "calibration-data";
+
+ svs_cpu_little: svs-cpu-little {
+ compatible = "mediatek,mt8183-svs-cpu-little";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ svs_cpu_big: svs-cpu-big {
+ compatible = "mediatek,mt8183-svs-cpu-big";
+ operating-points-v2 = <&cluster1_opp>;
+ };
+
+ svs_cci: svs-cci {
+ compatible = "mediatek,mt8183-svs-cci";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ svs_gpu: svs-gpu {
+ compatible = "mediatek,mt8183-svs-gpu";
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8183-i2c";
reg = <0 0x1100f000 0 0x1000>,
@@ -580,6 +613,14 @@
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+ svs_calibration: calib@580 {
+ reg = <0x580 0x64>;
+ };
};
mfgcfg: syscon@13000000 {
--
2.18.0
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next prev parent reply other threads:[~2020-01-07 7:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-07 7:01 PM / AVS: SVS: Introduce SVS engine Roger Lu
2020-01-07 7:01 ` [PATCH v6 1/3] dt-bindings: soc: add mtk svs dt-bindings Roger Lu
2020-01-08 20:38 ` Rob Herring
2020-01-13 6:44 ` Nicolas Boichat
2020-01-13 15:50 ` Rob Herring
2020-02-11 7:36 ` Roger Lu
2020-02-27 3:55 ` Nicolas Boichat
2020-04-08 5:58 ` Nicolas Boichat
2020-01-07 7:01 ` Roger Lu [this message]
2020-01-07 7:01 ` [PATCH v6 3/3] PM / AVS: SVS: Introduce SVS engine Roger Lu
2020-01-08 11:12 ` Pi-Hsun Shih
2020-01-09 5:02 ` Roger Lu
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