From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: drinkcat@chromium.org, weiyi.lu@mediatek.com,
fparent@baylibre.com, Matthias Brugger <mbrugger@suse.com>,
linux-mediatek@lists.infradead.org, hsinyi@chromium.org,
matthias.bgg@gmail.com,
Collabora Kernel ML <kernel@collabora.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 07/12] soc: mediatek: pm-domains: Add extra sram control
Date: Thu, 10 Sep 2020 19:28:21 +0200 [thread overview]
Message-ID: <20200910172826.3074357-8-enric.balletbo@collabora.com> (raw)
In-Reply-To: <20200910172826.3074357-1-enric.balletbo@collabora.com>
From: Matthias Brugger <mbrugger@suse.com>
For some power domains like vpu_core on MT8183 whose sram need to do clock
and internal isolation while power on/off sram. We add a cap
"MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation
control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 3aa430a60602..0802eccc3a0b 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -21,6 +21,7 @@
#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
#define MTK_SCPD_FWAIT_SRAM BIT(1)
+#define MTK_SCPD_SRAM_ISO BIT(2)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -42,6 +43,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_DISP BIT(3)
#define PWR_STATUS_MFG BIT(4)
@@ -162,6 +165,14 @@ static int scpsys_sram_enable(struct scpsys_domain *pd, void __iomem *ctl_addr)
if (ret < 0)
return ret;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -171,8 +182,15 @@ static int scpsys_sram_disable(struct scpsys_domain *pd, void __iomem *ctl_addr)
u32 val;
int tmp;
- val = readl(ctl_addr);
- val |= pd->data->sram_pdn_bits;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {
+ val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
+ val = readl(ctl_addr) | pd->data->sram_pdn_bits;
writel(val, ctl_addr);
/* Either wait until SRAM_PDN_ACK all 1 or 0 */
--
2.28.0
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next prev parent reply other threads:[~2020-09-10 17:30 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 17:28 [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 01/12] dt-bindings: power: Add bindings for the Mediatek " Enric Balletbo i Serra
2020-09-11 23:02 ` Rob Herring
2020-09-14 8:59 ` Matthias Brugger
2020-09-14 9:49 ` Enric Balletbo i Serra
2020-09-22 22:36 ` Rob Herring
2020-09-23 16:12 ` Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 02/12] soc: mediatek: Add MediaTek SCPSYS power domains Enric Balletbo i Serra
2020-09-25 10:25 ` Weiyi Lu
2020-09-25 10:43 ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 03/12] arm64: dts: mediatek: Add mt8173 power domain controller Enric Balletbo i Serra
2020-09-18 20:20 ` Fabien Parent
2020-09-18 20:50 ` Enric Balletbo Serra
2020-09-10 17:28 ` [PATCH 04/12] soc: mediatek: pm-domains: Add bus protection protocol Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 05/12] soc: mediatek: pm_domains: Make bus protection generic Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 06/12] soc: mediatek: pm-domains: Add SMI block as bus protection block Enric Balletbo i Serra
2020-09-25 10:45 ` Weiyi Lu
2020-09-25 11:01 ` Matthias Brugger
2020-09-10 17:28 ` Enric Balletbo i Serra [this message]
2020-09-10 18:27 ` [PATCH 07/12] soc: mediatek: pm-domains: Add extra sram control Matthias Brugger
2020-10-26 15:16 ` Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 08/12] soc: mediatek: pm-domains: Add subsystem clocks Enric Balletbo i Serra
2020-09-25 10:55 ` Weiyi Lu
2020-09-25 12:20 ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 09/12] soc: mediatek: pm-domains: Allow bus protection to ignore clear ack Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 10/12] dt-bindings: power: Add MT8183 power domains Enric Balletbo i Serra
2020-09-10 17:28 ` [PATCH 11/12] soc: mediatek: pm-domains: Add support for mt8183 Enric Balletbo i Serra
2020-09-16 9:46 ` Matthias Brugger
2020-09-16 12:19 ` Matthias Brugger
2020-09-25 7:37 ` Hsin-Yi Wang
2020-09-25 8:21 ` Enric Balletbo i Serra
2020-09-25 9:07 ` Matthias Brugger
2020-09-10 17:28 ` [PATCH 12/12] arm64: dts: mediatek: Add mt8183 power domains controller Enric Balletbo i Serra
2020-09-25 10:06 ` [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS " Weiyi Lu
2020-09-25 14:04 ` Matthias Brugger
2020-10-06 6:53 ` Weiyi Lu
2020-10-09 12:50 ` Matthias Brugger
2020-10-09 13:57 ` Enric Balletbo i Serra
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