From: Huacai Chen <chenhc@lemote.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: John Crispin <john@phrozen.org>,
"Steven J . Hill" <Steven.Hill@imgtec.com>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Huacai Chen <chenhc@lemote.com>,
stable@vger.kernel.org
Subject: [PATCH RESEND 1/4] MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2
Date: Sat, 21 Jan 2017 08:56:03 +0800 [thread overview]
Message-ID: <1484960166-30022-1-git-send-email-chenhc@lemote.com> (raw)
Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add
MIPS_CPU_FTLB to the CPU options.
Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/kernel/cpu-probe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 07718bb..12422fd 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
}
decode_configs(c);
- c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+ c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
break;
default:
--
2.7.0
next reply other threads:[~2017-01-21 0:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-21 0:56 Huacai Chen [this message]
2017-01-21 0:56 ` [PATCH RESEND 2/4] MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3 Huacai Chen
2017-01-21 0:56 ` [PATCH RESEND 3/4] MIPS: Flush wrong invalid FTLB entry for huge page Huacai Chen
2017-01-21 0:56 ` [PATCH RESEND 4/4] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
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