From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhc@lemote.com>, Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Mauro Carvalho Chehab <mchehab+samsung@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v8 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller
Date: Wed, 25 Mar 2020 11:54:54 +0800 [thread overview]
Message-ID: <20200325035537.156911-2-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20200325035537.156911-1-jiaxun.yang@flygoat.com>
This controller appeared on Loongson family of chips as the primary
package interrupt source.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
---
v4-v5:
Resolve suggestions from maz:
- Remove DT validation
- Simplify unnucessary functions & variables
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-liointc.c | 261 +++++++++++++++++++++++++
3 files changed, 271 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6d397732138d..c609eaa319d2 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config LOONGSON_LIOINTC
+ bool "Loongson Local I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson Local I/O Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eae0d78cbf22..5e7678efdfe6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
new file mode 100644
index 000000000000..18de2c09ece4
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
+ * Loongson Local IO Interrupt Controller support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include <boot_param.h>
+
+#define LIOINTC_CHIP_IRQ 32
+#define LIOINTC_NUM_PARENT 4
+
+#define LIOINTC_INTC_CHIP_START 0x20
+
+#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
+
+#define LIOINTC_SHIFT_INTx 4
+
+struct liointc_handler_data {
+ struct liointc_priv *priv;
+ u32 parent_int_map;
+};
+
+struct liointc_priv {
+ struct irq_chip_generic *gc;
+ struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
+ u8 map_cache[LIOINTC_CHIP_IRQ];
+};
+
+static void liointc_chained_handle_irq(struct irq_desc *desc)
+{
+ struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct irq_chip_generic *gc = handler->priv->gc;
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void liointc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int liointc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static void liointc_resume(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Disable all at first */
+ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
+ /* Revert map cache */
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i], gc->reg_base + i);
+ /* Revert mask cache */
+ writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
+
+int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct liointc_priv *priv;
+ void __iomem *base;
+ u32 of_parent_int_map[LIOINTC_NUM_PARENT];
+ int parent_irq[LIOINTC_NUM_PARENT];
+ bool have_parent = FALSE;
+ int sz, i, err = 0;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent) {
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ sz = of_property_read_variable_u32_array(node,
+ "loongson,parent_int_map",
+ &of_parent_int_map[0],
+ LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = of_parent_int_map[i];
+
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &irq_generic_chip_ops, priv);
+ if (!domain) {
+ pr_err("loongson-liointc: cannot add IRQ domain\n");
+ err = -EINVAL;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name, handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("loongson-liointc: unable to register IRQ domain\n");
+ goto out_free_domain;
+ }
+
+
+ /* Disable all IRQs */
+ writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, base + LIOINTC_REG_INTC_EDGE);
+
+ /* Generate parent INT part of map cache */
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ u32 pending = priv->handler[i].parent_int_map;
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
+ pending &= ~BIT(bit);
+ }
+ }
+
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
+ /* Generate core part of map cache */
+ priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
+ writeb(priv->map_cache[i], base + i);
+ }
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = base;
+ gc->domain = domain;
+ gc->resume = liointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
+ ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = liointc_set_type;
+
+ gc->mask_cache = 0xffffffff;
+ priv->gc = gc;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ if (parent_irq[i] <= 0)
+ continue;
+
+ priv->handler[i].priv = priv;
+ irq_set_chained_handler_and_data(parent_irq[i],
+ liointc_chained_handle_irq, &priv->handler[i]);
+ }
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
+IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
--
2.26.0.rc2
next prev parent reply other threads:[~2020-03-25 3:57 UTC|newest]
Thread overview: 175+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 8:52 [PATCH 00/13] Modernize Loongson64 Machine Jiaxun Yang
2019-08-27 8:52 ` [PATCH 01/13] MIPS: Loongson64: Rename CPU TYPES Jiaxun Yang
2019-08-27 8:52 ` [PATCH 02/13] MIPS: Loongson64: Sepreate loongson2ef/loongson64 code Jiaxun Yang
2019-08-27 22:05 ` Aaro Koskinen
2019-08-28 0:37 ` Jiaxun Yang
2019-09-02 17:51 ` Aaro Koskinen
2019-08-27 8:52 ` [PATCH 03/13] MAINTAINERS: Fix entries for new loongson64 path Jiaxun Yang
2019-08-27 8:52 ` [PATCH 04/13] irqchip: Add driver for Loongson-3 I/O interrupt controller Jiaxun Yang
2019-08-27 16:45 ` Marc Zyngier
2019-08-28 0:27 ` Jiaxun Yang
2019-08-28 6:59 ` Marc Zyngier
2019-08-28 15:31 ` Jiaxun Yang
2019-08-28 16:02 ` Marc Zyngier
2019-08-27 8:52 ` [PATCH 05/13] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
2019-08-27 13:08 ` Rob Herring
2019-08-27 8:52 ` [PATCH 06/13] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Jiaxun Yang
2019-08-27 12:53 ` Marc Zyngier
2019-08-27 8:52 ` [PATCH 07/13] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Jiaxun Yang
2019-08-27 12:49 ` Rob Herring
2019-08-27 14:08 ` Jiaxun Yang
2019-08-27 8:52 ` [PATCH 08/13] irqchip: i8259: Add plat-poll support Jiaxun Yang
2019-08-27 8:52 ` [PATCH 09/13] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2019-08-27 8:52 ` [PATCH 10/13] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2019-08-27 8:53 ` [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards Jiaxun Yang
2019-08-27 12:45 ` Rob Herring
2019-08-27 14:18 ` Jiaxun Yang
2019-08-27 20:41 ` Paul Burton
2019-08-28 0:15 ` Jiaxun Yang
2019-09-02 14:50 ` Rob Herring
2019-09-03 9:07 ` Paul Burton
2019-09-04 3:33 ` Huacai Chen
2019-08-27 8:53 ` [PATCH 12/13] MIPS: Loongson64: Add generic dts Jiaxun Yang
2019-08-27 8:53 ` [PATCH 13/13] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2019-08-27 13:25 ` Re:[PATCH 00/13] Modernize Loongson64 Machine 陈华才
2019-08-27 14:39 ` [PATCH " Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 00/18] " Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 01/18] MIPS: Loongson64: Rename CPU TYPES Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 02/18] MIPS: Loongson64: separate loongson2ef/loongson64 code Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 03/18] MAINTAINERS: Fix entries for new loongson64 path Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 04/18] irqchip: Export generic chip domain map/unmap functions Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 05/18] irqchip: Add driver for Loongson-3 I/O interrupt controller Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 06/18] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
2019-09-05 14:42 ` [PATCH v2 00/19] Modernize Loongson64 Machine Jiaxun Yang
2019-09-05 14:42 ` [PATCH v2 01/19] MIPS: Loongson64: Rename CPU TYPES Jiaxun Yang
2019-09-05 14:42 ` [PATCH v2 02/19] MIPS: Loongson64: separate loongson2ef/loongson64 code Jiaxun Yang
2019-09-10 0:12 ` Paul Burton
2019-09-16 2:23 ` Huacai Chen
2019-09-18 0:38 ` Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 03/19] MAINTAINERS: Fix entries for new loongson64 path Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 04/19] irqchip: Export generic chip domain map/unmap functions Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 05/19] irqchip: Add driver for Loongson-3 I/O interrupt controller Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 06/19] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
2019-09-17 21:26 ` Rob Herring
2019-09-05 14:43 ` [PATCH v2 07/19] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 08/19] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 09/19] irqchip: i8259: Add plat-poll support Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 10/19] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 11/19] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 12/19] dt-bindings: mips: Add loongson boards Jiaxun Yang
2019-09-30 13:23 ` Rob Herring
2019-09-05 14:43 ` [PATCH v2 13/19] dt-bindings: Document loongson vendor-prefix Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 14/19] MIPS: Loongson64: Add generic dts Jiaxun Yang
2019-09-07 2:53 ` Huacai Chen
2019-09-07 3:14 ` Jiaxun Yang
2019-09-30 13:20 ` Rob Herring
2019-09-05 14:43 ` [PATCH v2 15/19] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 16/19] GPIO: loongson: Drop Loongson-3A/3B support Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 17/19] MIPS: Loongson: Regenerate defconfigs Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 18/19] MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE Jiaxun Yang
2019-09-05 14:43 ` [PATCH v2 19/19] MAINTAINERS: Add myself as maintainer of LOONGSON64 Jiaxun Yang
2019-09-07 3:13 ` [PATCH v2 00/19] Modernize Loongson64 Machine Huacai Chen
2019-09-12 6:30 ` [PATCH 00/13] " Matt Turner
2019-09-18 0:33 ` Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 00/10] " Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 01/10] dt-bindings: Document loongson vendor-prefix Jiaxun Yang
2020-01-15 18:59 ` Paul Burton
2020-01-12 8:14 ` [PATCH v3 02/10] irqchip: Add driver for Loongson I/O interrupt controller Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 03/10] dt-bindings: interrupt-controller: Add Loongson IOINTC Jiaxun Yang
2020-01-13 3:44 ` Huacai Chen
2020-01-13 3:40 ` Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 04/10] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 05/10] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 06/10] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 07/10] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 08/10] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-01-13 3:39 ` Huacai Chen
2020-01-12 8:14 ` [PATCH v3 09/10] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-01-12 8:14 ` [PATCH v3 10/10] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-01-13 3:38 ` [PATCH v3 00/10] Modernize Loongson64 Machine Huacai Chen
2020-02-21 5:09 ` [PATCH v4 00/10] Modernize Loongson64 Machine v4 Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 01/10] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-02-29 2:30 ` 回复:[PATCH " Jiaxun Yang
2020-03-07 14:50 ` [PATCH " Marc Zyngier
2020-02-21 5:09 ` [PATCH v4 02/10] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 03/10] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-07 15:01 ` Marc Zyngier
2020-02-21 5:09 ` [PATCH v4 04/10] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 05/10] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 06/10] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 07/10] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-02-26 16:52 ` Rob Herring
2020-02-29 2:28 ` Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 08/10] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 09/10] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-02-21 5:09 ` [PATCH v4 10/10] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 00/11] Modernize Loongson64 Machine v5 Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 04/11] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-21 14:14 ` Marc Zyngier
2020-03-18 6:20 ` [PATCH v5 05/11] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 06/11] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 07/11] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 08/11] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-03-20 22:36 ` Rob Herring
2020-03-22 5:33 ` Zhou Yanjie
2020-03-18 6:20 ` [PATCH v5 09/11] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 10/11] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-03-18 6:20 ` [PATCH v5 11/11] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Jiaxun Yang
2020-03-24 15:35 ` [PATCH v6 00/11] Modernize Loongson64 Machine v6 Jiaxun Yang
2020-03-24 15:35 ` [PATCH v6 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-24 15:35 ` [PATCH v6 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-25 1:52 ` Huacai Chen
2020-03-25 2:31 ` Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 04/11] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 05/11] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 06/11] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 07/11] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 08/11] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 09/11] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-03-25 2:11 ` Huacai Chen
2020-03-25 2:08 ` Jiaxun Yang
2020-03-25 2:49 ` Huacai Chen
2020-03-24 15:36 ` [PATCH v6 10/11] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-03-24 15:36 ` [PATCH v6 11/11] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Jiaxun Yang
2020-03-24 15:47 ` [PATCH v6 00/11] Modernize Loongson64 Machine v6 Marc Zyngier
2020-03-24 15:51 ` Jiaxun Yang
2020-03-24 18:07 ` Thomas Bogendoerfer
2020-03-25 2:28 ` [PATCH v7 00/12] " Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 01/12] irqchip: Add driver for Loongson I/O Local Interrupt Controller Jiaxun Yang
2020-03-25 11:25 ` Paul Cercueil
2020-03-25 11:35 ` Marc Zyngier
2020-03-25 2:28 ` [PATCH v7 01/12] MIPS: Loongson: Do not initialise statics to 0 Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 02/12] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 02/12] MIPS: DTS: CI20: add DT node for IR sensor Jiaxun Yang
2020-03-25 2:28 ` [PATCH v7 03/12] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 00/11] Modernize Loongson64 Machine v8 Jiaxun Yang
2020-03-25 3:54 ` Jiaxun Yang [this message]
2020-03-25 3:54 ` [PATCH v8 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 04/11] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 05/11] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Jiaxun Yang
2020-03-25 3:54 ` [PATCH v8 06/11] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-25 12:37 ` Thomas Bogendoerfer
2020-03-25 12:48 ` Jiaxun Yang
2020-03-25 13:00 ` Marc Zyngier
2020-03-25 13:07 ` Jiaxun Yang
2020-03-25 13:57 ` Marc Zyngier
2020-03-25 13:59 ` Jiaxun Yang
2020-03-25 14:15 ` Marc Zyngier
2020-03-25 14:31 ` Jiaxun Yang
2020-03-25 15:02 ` Marc Zyngier
2020-03-25 15:04 ` Thomas Bogendoerfer
2020-03-25 15:09 ` Jiaxun Yang
2020-03-25 15:46 ` Thomas Bogendoerfer
2020-03-25 16:02 ` Jiaxun Yang
2020-03-25 16:31 ` Thomas Bogendoerfer
2020-03-25 3:55 ` [PATCH v8 07/11] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 08/11] dt-bindings: mips: Add loongson boards Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 09/11] MIPS: Loongson64: Add generic dts Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 10/11] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2020-03-25 3:55 ` [PATCH v8 11/11] MAINTAINERS: Update Loongson64 entry Jiaxun Yang
2020-03-25 17:33 ` [PATCH v8 00/11] Modernize Loongson64 Machine v8 Thomas Bogendoerfer
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