linux-mips.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: tsbogend@alpha.franken.de, maz@kernel.org, chenhc@lemote.com,
	Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [RFC PATCH 2/6] irqchip: mips-cpu: Allocate fwnode for non-DT platforms
Date: Thu, 26 Mar 2020 14:16:59 +0800	[thread overview]
Message-ID: <20200326061704.387483-4-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20200326061704.387483-1-jiaxun.yang@flygoat.com>

fwnode is required by fwspec based domain opreations to match domains.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/irqchip/irq-mips-cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 19734b11b36d..e029e0fe2ee2 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -247,6 +247,8 @@ static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {}
 
 static void __init __mips_cpu_irq_init(struct device_node *of_node)
 {
+	struct fwnode_handle *fwnode;
+
 	/* Mask interrupts. */
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
@@ -257,6 +259,14 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
 	if (!mips_cpu_irq_domain)
 		panic("Failed to add irqdomain for MIPS CPU");
 
+	if (!of_node) {
+		fwnode = irq_domain_alloc_named_fwnode("MIPS-CPU-IRQ");
+		if (!fwnode)
+			panic("Failed to allocate fwnode for MIPS CPU IRQ");
+		mips_cpu_irq_domain->fwnode = fwnode;
+		mips_cpu_irq_domain->name = kstrdup("MIPS-CPU-IRQ", GFP_KERNEL);
+	}
+
 	/*
 	 * Only proceed to register the software interrupt IPI implementation
 	 * for CPUs which implement the MIPS MT (multi-threading) ASE.
-- 
2.26.0.rc2



  parent reply	other threads:[~2020-03-26  6:18 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-26  6:16 [RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way Jiaxun Yang
2020-03-26  6:16 ` [RFC PATCH 1/6] MIPS: irq_cpu: Add a helper to map virq for CPU IRQ Jiaxun Yang
2020-03-26  6:16 ` [PATCH 1/2] MIPS: Kill MIPS_GIC_IRQ_BASE Jiaxun Yang
2020-03-26  6:16 ` Jiaxun Yang [this message]
2020-03-26  6:17 ` [PATCH 2/2] MIPS: Kill RM7K & RM9K IRQ Code Jiaxun Yang
2020-03-26  6:17 ` [RFC PATCH 3/6] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-26  6:17 ` [RFC PATCH 4/6] MIPS: kernel: Use mips_cpu_map_virq helper Jiaxun Yang
2020-03-26  6:17 ` [RFC PATCH 5/6] MIPS: loongson64: " Jiaxun Yang
2020-03-26  6:20 ` [RFC PATCH 6/6] MIPS: ip22: " Jiaxun Yang
2020-03-26 15:38 ` [RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way Thomas Bogendoerfer
2020-03-26 15:46   ` Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200326061704.387483-4-jiaxun.yang@flygoat.com \
    --to=jiaxun.yang@flygoat.com \
    --cc=chenhc@lemote.com \
    --cc=linux-mips@vger.kernel.org \
    --cc=maz@kernel.org \
    --cc=tsbogend@alpha.franken.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).