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From: <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Paul Burton <paulburton@kernel.org>,
	Ralf Baechle <ralf@linux-mips.org>, Arnd Bergmann <arnd@arndb.de>,
	Rob Herring <robh+dt@kernel.org>, <linux-pm@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	Allison Randal <allison@lohutok.net>,
	Thomas Gleixner <tglx@linutronix.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<linux-mips@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting
Date: Wed, 6 May 2020 20:42:23 +0300	[thread overview]
Message-ID: <20200506174238.15385-6-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru>

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

According to the MIPS32 InterAptiv software manual error codes 24 - 26
of CM2 indicate L2 ECC/parity error with switching to a corresponding
errors info fields. This patch provides these errors parsing code,
which handles the read/write uncorrectable and correctable ECC/parity
errors, and prints instruction causing the fault, RAM array type, cache
way/dword and syndrome associated with the faulty data.

Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-pm@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/kernel/mips-cm.c | 62 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 60 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index 361bfc91a0e6..f60af512c877 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -114,6 +114,48 @@ static char *cm2_core[8] = {
 	"Exclusive/OK", "Exclusive/Data"
 };
 
+static char *cm2_l2_type[4] = {
+	[0x0] = "None",
+	[0x1] = "Tag RAM single/double ECC error",
+	[0x2] = "Data RAM single/double ECC error",
+	[0x3] = "WS RAM uncorrectable dirty parity"
+};
+
+static char *cm2_l2_instr[32] = {
+	[0x00] = "L2_NOP",
+	[0x01] = "L2_ERR_CORR",
+	[0x02] = "L2_TAG_INV",
+	[0x03] = "L2_WS_CLEAN",
+	[0x04] = "L2_RD_MDYFY_WR",
+	[0x05] = "L2_WS_MRU",
+	[0x06] = "L2_EVICT_LN2",
+	[0x07] = "0x07",
+	[0x08] = "L2_EVICT",
+	[0x09] = "L2_REFL",
+	[0x0a] = "L2_RD",
+	[0x0b] = "L2_WR",
+	[0x0c] = "L2_EVICT_MRU",
+	[0x0d] = "L2_SYNC",
+	[0x0e] = "L2_REFL_ERR",
+	[0x0f] = "0x0f",
+	[0x10] = "L2_INDX_WB_INV",
+	[0x11] = "L2_INDX_LD_TAG",
+	[0x12] = "L2_INDX_ST_TAG",
+	[0x13] = "L2_INDX_ST_DATA",
+	[0x14] = "L2_INDX_ST_ECC",
+	[0x15] = "0x15",
+	[0x16] = "0x16",
+	[0x17] = "0x17",
+	[0x18] = "L2_FTCH_AND_LCK",
+	[0x19] = "L2_HIT_INV",
+	[0x1a] = "L2_HIT_WB_INV",
+	[0x1b] = "L2_HIT_WB",
+	[0x1c] = "0x1c",
+	[0x1d] = "0x1d",
+	[0x1e] = "0x1e",
+	[0x1f] = "0x1f"
+};
+
 static char *cm2_causes[32] = {
 	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
 	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
@@ -121,7 +163,7 @@ static char *cm2_causes[32] = {
 	"0x0c", "0x0d", "0x0e", "0x0f",
 	"0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
 	"0x14", "0x15", "0x16", "0x17",
-	"0x18", "0x19", "0x1a", "0x1b",
+	"L2_RD_UNCORR", "L2_WR_UNCORR", "L2_CORR", "0x1b",
 	"0x1c", "0x1d", "0x1e", "0x1f"
 };
 
@@ -360,7 +402,7 @@ void mips_cm_error_report(void)
 				 "CCA=%lu TR=%s MCmd=%s STag=%lu "
 				 "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
 				 cm2_cmd[cmd_bits], stag_bits, sport_bits);
-		} else {
+		} else if (cause < 24) {
 			/* glob state & sresp together */
 			unsigned long c3_bits = (cm_error >> 18) & 7;
 			unsigned long c2_bits = (cm_error >> 15) & 7;
@@ -377,6 +419,22 @@ void mips_cm_error_report(void)
 				 cm2_core[c1_bits], cm2_core[c0_bits],
 				 sc_bit ? "True" : "False",
 				 cm2_cmd[cmd_bits], sport_bits);
+		} else {
+			unsigned long muc_bit = (cm_error >> 23) & 1;
+			unsigned long ins_bits = (cm_error >> 18) & 0x1f;
+			unsigned long arr_bits = (cm_error >> 16) & 3;
+			unsigned long dw_bits = (cm_error >> 12) & 15;
+			unsigned long way_bits = (cm_error >> 9) & 7;
+			unsigned long mway_bit = (cm_error >> 8) & 1;
+			unsigned long syn_bits = (cm_error >> 0) & 0xFF;
+
+			snprintf(buf, sizeof(buf),
+				 "Type=%s%s Instr=%s DW=%lu Way=%lu "
+				 "MWay=%s Syndrome=0x%02lx",
+				 muc_bit ? "Multi-UC " : "",
+				 cm2_l2_type[arr_bits],
+				 cm2_l2_instr[ins_bits], dw_bits, way_bits,
+				 mway_bit ? "True" : "False", syn_bits);
 		}
 		pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
 		       cm2_causes[cause], buf);
-- 
2.25.1


  parent reply	other threads:[~2020-05-06 17:49 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-06 12:46 [PATCH 00/22] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 00/20] " Sergey.Semin
2020-05-06 17:42   ` [PATCH v2 01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema Sergey.Semin
2020-05-14 15:09     ` Rob Herring
2020-05-14 18:04       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 02/20] dt-bindings: bus: Add MIPS CDMM controller Sergey.Semin
2020-05-14 15:09     ` Rob Herring
2020-05-14 18:05       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 03/20] dt-bindings: Add vendor prefix for Baikal Electronics, JSC Sergey.Semin
2020-05-06 17:55     ` Sam Ravnborg
2020-05-06 19:20       ` Serge Semin
2020-05-06 19:26         ` Sam Ravnborg
2020-05-06 20:18           ` Serge Semin
2020-05-14 18:13     ` Serge Semin
2020-05-14 18:31     ` Rob Herring
2020-05-06 17:42   ` [PATCH v2 04/20] mips: cm: Fix an invalid error code of INTVN_*_ERR Sergey.Semin
2020-05-07 11:10     ` Thomas Bogendoerfer
2020-05-07 21:32       ` Serge Semin
2020-05-06 17:42   ` Sergey.Semin [this message]
2020-05-07 11:17     ` [PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting Thomas Bogendoerfer
2020-05-07 21:38       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 06/20] mips: Add MIPS32 Release 5 support Sergey.Semin
2020-05-08 13:30     ` Thomas Bogendoerfer
2020-05-10 22:05       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support Sergey.Semin
2020-05-07 11:17     ` Thomas Bogendoerfer
2020-05-07 21:19       ` Serge Semin
2020-05-08  9:32         ` Thomas Bogendoerfer
2020-05-08 12:21           ` Thomas Bogendoerfer
2020-05-10 22:09             ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 08/20] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Sergey.Semin
2020-05-08 13:28     ` Thomas Bogendoerfer
2020-05-10 23:59       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 09/20] mips: Add CP0 Write Merge config support Sergey.Semin
2020-05-06 17:42   ` [PATCH v2 10/20] mips: Add CONFIG/CONFIG6/Cause reg fields macro Sergey.Semin
2020-05-06 17:42   ` [PATCH v2 11/20] mips: MAAR: Use more precise address mask Sergey.Semin
2020-05-07 11:09     ` Thomas Bogendoerfer
2020-05-07 19:13       ` Serge Semin
2020-05-08  9:22         ` Thomas Bogendoerfer
2020-05-10 22:13           ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 12/20] mips: MAAR: Add XPA mode support Sergey.Semin
2020-05-19 15:42     ` Thomas Bogendoerfer
2020-05-20 11:30       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 13/20] mips: early_printk_8250: Use offset-sized IO-mem accessors Sergey.Semin
2020-05-06 17:42   ` [PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout Sergey.Semin
2020-05-06 18:16     ` Sergei Shtylyov
2020-05-06 19:52       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 15/20] mips: cdmm: Add mti,mips-cdmm dtb node support Sergey.Semin
2020-05-06 17:42   ` [PATCH v2 16/20] bus: cdmm: Add MIPS R5 arch support Sergey.Semin
2020-05-06 17:42   ` [PATCH v2 17/20] mips: Add udelay lpj numbers adjustment Sergey.Semin
2020-05-08 12:15     ` Jiaxun Yang
2020-05-06 17:42   ` [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled Sergey.Semin
2020-05-08 15:41     ` Thomas Bogendoerfer
2020-05-11 13:31       ` Serge Semin
2020-05-15  7:48         ` Serge Semin
2020-05-15 21:06           ` Thomas Bogendoerfer
2020-05-16 11:55             ` Serge Semin
2020-05-18 13:48             ` Serge Semin
2020-05-18 16:32               ` Thomas Bogendoerfer
2020-05-18 20:57                 ` Serge Semin
2020-05-19 15:50                   ` Thomas Bogendoerfer
2020-05-20 11:59                     ` Serge Semin
2020-05-20 14:03                       ` Serge Semin
2020-05-20 18:40                       ` Thomas Bogendoerfer
2020-05-20 21:13                         ` Serge Semin
2020-05-20 12:12                     ` Serge Semin
2020-05-20 12:21                       ` Serge Semin
2020-05-20 13:38                       ` Thomas Bogendoerfer
2020-05-20 13:48                         ` Serge Semin
2020-05-20 18:30                           ` Thomas Bogendoerfer
2020-05-20 21:12                             ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 19/20] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Sergey.Semin
2020-05-08 15:40     ` Thomas Bogendoerfer
2020-05-11  0:34       ` Serge Semin
2020-05-06 17:42   ` [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting Sergey.Semin
2020-05-15 15:58     ` Rafael J. Wysocki
2020-05-16 12:52       ` Serge Semin
2020-05-18  7:41         ` Viresh Kumar
2020-05-18  9:53           ` Rafael J. Wysocki
2020-05-18 10:11             ` Viresh Kumar
2020-05-18 10:22               ` Rafael J. Wysocki
2020-05-18 10:24                 ` Viresh Kumar
2020-05-18 10:31                   ` Serge Semin
2020-05-18 10:41                     ` Rafael J. Wysocki
2020-05-18 10:46                       ` Serge Semin
2020-05-18 10:51                         ` Rafael J. Wysocki
2020-05-18 10:56                           ` Serge Semin
2020-05-18 11:05                             ` Rafael J. Wysocki
2020-05-19  1:50                               ` Xiongfeng Wang

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