From: Paul Cercueil <paul@crapouillou.net>
To: 周琰杰 <zhouyanjie@wanyeetech.com>
Cc: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org,
linux-clk@vger.kernel.org, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com,
rick.tyliu@ingenic.com, sihui.liu@ingenic.com,
jun.jiang@ingenic.com, sernia.zhou@foxmail.com
Subject: Re: [PATCH v7 08/11] dt-bindings: clock: Add JZ4775 clock bindings.
Date: Thu, 19 Aug 2021 11:47:36 +0200 [thread overview]
Message-ID: <C7Z2YQ.GPU7ZNCXXLGH1@crapouillou.net> (raw)
In-Reply-To: <1627119286-125821-9-git-send-email-zhouyanjie@wanyeetech.com>
Hi Zhou,
Le sam., juil. 24 2021 at 17:34:43 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> Add the clock bindings for the JZ4775 SoC from Ingenic.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> ---
>
> Notes:
> v5:
> New patch.
>
> v5->v6:
> No change.
>
> v6->v7:
> Change to dual license.
>
> include/dt-bindings/clock/jz4775-cgu.h | 59
> ++++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 include/dt-bindings/clock/jz4775-cgu.h
>
> diff --git a/include/dt-bindings/clock/jz4775-cgu.h
> b/include/dt-bindings/clock/jz4775-cgu.h
> new file mode 100644
> index 00000000..4625418
> --- /dev/null
> +++ b/include/dt-bindings/clock/jz4775-cgu.h
> @@ -0,0 +1,59 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * This header provides clock numbers for the ingenic,jz4775-cgu DT
> binding.
> + *
> + * They are roughly ordered as:
> + * - external clocks
> + * - PLLs
> + * - muxes/dividers in the order they appear in the jz4775
> programmers manual
> + * - gates in order of their bit in the CLKGR* registers
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_JZ4775_CGU_H__
> +#define __DT_BINDINGS_CLOCK_JZ4775_CGU_H__
> +
> +#define JZ4775_CLK_EXCLK 0
> +#define JZ4775_CLK_RTCLK 1
> +#define JZ4775_CLK_APLL 2
> +#define JZ4775_CLK_MPLL 3
> +#define JZ4775_CLK_OTGPHY 4
> +#define JZ4775_CLK_SCLKA 5
> +#define JZ4775_CLK_UHC 6
> +#define JZ4775_CLK_UHCPHY 7
> +#define JZ4775_CLK_CPUMUX 8
> +#define JZ4775_CLK_CPU 9
> +#define JZ4775_CLK_L2CACHE 10
> +#define JZ4775_CLK_AHB0 11
> +#define JZ4775_CLK_AHB2PMUX 12
> +#define JZ4775_CLK_AHB2 13
> +#define JZ4775_CLK_PCLK 14
> +#define JZ4775_CLK_DDR 15
> +#define JZ4775_CLK_VPU 16
> +#define JZ4775_CLK_OTG 17
> +#define JZ4775_CLK_EXCLK_DIV2 18
> +#define JZ4775_CLK_I2S 19
> +#define JZ4775_CLK_LCD 20
> +#define JZ4775_CLK_MSCMUX 21
> +#define JZ4775_CLK_MSC0 22
> +#define JZ4775_CLK_MSC1 23
> +#define JZ4775_CLK_MSC2 24
> +#define JZ4775_CLK_SSI 25
> +#define JZ4775_CLK_CIM0 26
> +#define JZ4775_CLK_CIM1 27
> +#define JZ4775_CLK_PCM 28
> +#define JZ4775_CLK_BCH 29
> +#define JZ4775_CLK_EXCLK_DIV512 30
> +#define JZ4775_CLK_RTC 31
> +#define JZ4775_CLK_NEMC 32
> +#define JZ4775_CLK_I2C0 33
> +#define JZ4775_CLK_I2C1 34
> +#define JZ4775_CLK_I2C2 35
> +#define JZ4775_CLK_SADC 36
> +#define JZ4775_CLK_UART0 37
> +#define JZ4775_CLK_UART1 38
> +#define JZ4775_CLK_UART2 39
> +#define JZ4775_CLK_UART3 40
> +#define JZ4775_CLK_PDMA 41
> +#define JZ4775_CLK_MAC 42
> +
> +#endif /* __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ */
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-08-19 9:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-24 9:34 [PATCH v7 00/11] Add new clocks and fix bugs for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 01/11] clk: JZ4780: Add function for disable the second core 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 02/11] clk: Ingenic: Adjust cgu code to make it compatible with I2S PLL 周琰杰 (Zhou Yanjie)
2021-08-19 9:37 ` Paul Cercueil
2021-08-27 17:46 ` Zhou Yanjie
2021-07-24 9:34 ` [PATCH v7 03/11] dt-bindings: clock: Add missing clocks for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 04/11] clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830 周琰杰 (Zhou Yanjie)
2021-08-19 9:39 ` Paul Cercueil
2021-07-24 9:34 ` [PATCH v7 05/11] clk: Ingenic: Add missing clocks for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 06/11] clk: Ingenic: Clean up and reformat the code 周琰杰 (Zhou Yanjie)
2021-08-19 9:46 ` Paul Cercueil
2021-08-27 17:47 ` Zhou Yanjie
2021-07-24 9:34 ` [PATCH v7 07/11] dt-bindings: clock: Add documentation for JZ4775 and X2000 bindings 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 08/11] dt-bindings: clock: Add JZ4775 clock bindings 周琰杰 (Zhou Yanjie)
2021-07-26 22:18 ` Rob Herring
2021-08-19 9:47 ` Paul Cercueil [this message]
2021-07-24 9:34 ` [PATCH v7 09/11] dt-bindings: clock: Add X2000 " 周琰杰 (Zhou Yanjie)
2021-07-26 22:19 ` Rob Herring
2021-08-19 9:48 ` Paul Cercueil
2021-07-24 9:34 ` [PATCH v7 10/11] clk: Ingenic: Add CGU driver for JZ4775 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 11/11] clk: Ingenic: Add CGU driver for X2000 周琰杰 (Zhou Yanjie)
2021-08-19 6:44 ` [PATCH v7 00/11] Add new clocks and fix bugs for Ingenic SoCs Zhou Yanjie
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