From: Ingo Molnar <mingo@kernel.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCHv7 13/14] x86: Enable 5-level paging support
Date: Thu, 22 Jun 2017 11:24:54 +0200 [thread overview]
Message-ID: <20170622092454.n4f2uho5lsp6ox4q@gmail.com> (raw)
In-Reply-To: <20170606113133.22974-14-kirill.shutemov@linux.intel.com>
* Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote:
> Most of things are in place and we can enable support of 5-level paging.
>
> The patch makes XEN_PV dependent on !X86_5LEVEL. XEN_PV is not ready to
> work with 5-level paging.
Please make a short comment about that in the Kconfig code as well, instead of a
silent, undocumented 'depends' clause.
> config PGTABLE_LEVELS
> int
> + default 5 if X86_5LEVEL
> default 4 if X86_64
> default 3 if X86_PAE
> default 2
> @@ -1390,6 +1391,10 @@ config X86_PAE
> has the cost of more pagetable lookup overhead, and also
> consumes more pagetable space per process.
>
> +config X86_5LEVEL
> + bool "Enable 5-level page tables support"
> + depends on X86_64
So since users will be enabling it, this needs a proper help text that explains
what hardware supports it ("future Intel CPUs" will do if models are not public
yet), a short blurb about what it's good for - and a link to the Documentation/
file explaining it all.
Thanks,
Ingo
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next prev parent reply other threads:[~2017-06-22 9:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-06 11:31 [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4 Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 01/14] x86/mm/gup: Switch GUP to the generic get_user_page_fast() implementation Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 02/14] x86/asm: Fix comment in return_from_SYSCALL_64 Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 03/14] x86/boot/efi: Cleanup initialization of GDT entries Kirill A. Shutemov
2017-06-08 14:00 ` Matt Fleming
2017-06-06 11:31 ` [PATCHv7 04/14] x86/boot/efi: Fix __KERNEL_CS definition of GDT entry on 64-bit configuration Kirill A. Shutemov
2017-06-08 14:09 ` Matt Fleming
2017-06-06 11:31 ` [PATCHv7 05/14] x86/boot/efi: Define __KERNEL32_CS GDT on 64-bit configurations Kirill A. Shutemov
2017-06-08 14:18 ` Matt Fleming
2017-06-06 11:31 ` [PATCHv7 06/14] x86/boot/compressed: Enable 5-level paging during decompression stage Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 07/14] x86/boot/64: Rewrite startup_64 in C Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 08/14] x86/boot/64: Rename init_level4_pgt and early_level4_pgt Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 09/14] x86/boot/64: Add support of additional page table level during early boot Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 10/14] x86/mm: Add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 11/14] x86/mm: Make kernel_physical_mapping_init() support " Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 12/14] x86/mm: Add support for 5-level paging for KASLR Kirill A. Shutemov
2017-06-06 11:31 ` [PATCHv7 13/14] x86: Enable 5-level paging support Kirill A. Shutemov
2017-06-22 9:24 ` Ingo Molnar [this message]
2017-06-06 11:31 ` [PATCHv7 14/14] x86/mm: Allow to have userspace mappings above 47-bits Kirill A. Shutemov
2017-06-22 8:57 ` [PATCHv7 00/14] x86: 5-level paging enabling for v4.13, Part 4 Kirill A. Shutemov
2017-06-22 9:04 ` Ingo Molnar
2017-06-22 9:07 ` Kirill A. Shutemov
2017-06-22 9:21 ` Ingo Molnar
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