From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Linus Torvalds <torvalds@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>
Cc: Andrew Morton <akpm@linux-foundation.org>,
Andy Lutomirski <luto@amacapital.net>,
Dmitry Safonov <dsafonov@virtuozzo.com>,
Cyrill Gorcunov <gorcunov@openvz.org>,
Borislav Petkov <bp@suse.de>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCHv5 16/19] x86/mm: Allow to boot without la57 if CONFIG_X86_5LEVEL=y
Date: Mon, 21 Aug 2017 18:29:13 +0300 [thread overview]
Message-ID: <20170821152916.40124-17-kirill.shutemov@linux.intel.com> (raw)
In-Reply-To: <20170821152916.40124-1-kirill.shutemov@linux.intel.com>
All pieces of the puzzle are in place and we can now allow to boot with
CONFIG_X86_5LEVEL=y on a machine without la57 support.
Kernel will detect that la57 is missing and fold p4d at runtime.
Update documentation and Kconfig option description to reflect the
change.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
Documentation/x86/x86_64/5level-paging.txt | 9 +++------
arch/x86/Kconfig | 4 ++--
arch/x86/include/asm/required-features.h | 8 +-------
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/Documentation/x86/x86_64/5level-paging.txt b/Documentation/x86/x86_64/5level-paging.txt
index 087251a0d99c..2432a5ef86d9 100644
--- a/Documentation/x86/x86_64/5level-paging.txt
+++ b/Documentation/x86/x86_64/5level-paging.txt
@@ -20,12 +20,9 @@ Documentation/x86/x86_64/mm.txt
CONFIG_X86_5LEVEL=y enables the feature.
-So far, a kernel compiled with the option enabled will be able to boot
-only on machines that supports the feature -- see for 'la57' flag in
-/proc/cpuinfo.
-
-The plan is to implement boot-time switching between 4- and 5-level paging
-in the future.
+Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
+In this case additional page table level -- p4d -- will be folded at
+runtime.
== User-space and large virtual address space ==
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ac3358bb7bd2..939698570aa1 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1409,8 +1409,8 @@ config X86_5LEVEL
It will be supported by future Intel CPUs.
- Note: a kernel with this option enabled can only be booted
- on machines that support the feature.
+ A kernel with the option enabled can be booted on machines that
+ support 4- or 5-level paging.
See Documentation/x86/x86_64/5level-paging.txt for more
information.
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index d91ba04dd007..fac9a5c0abe9 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -53,12 +53,6 @@
# define NEED_MOVBE 0
#endif
-#ifdef CONFIG_X86_5LEVEL
-# define NEED_LA57 (1<<(X86_FEATURE_LA57 & 31))
-#else
-# define NEED_LA57 0
-#endif
-
#ifdef CONFIG_X86_64
#ifdef CONFIG_PARAVIRT
/* Paravirtualized systems may not have PSE or PGE available */
@@ -104,7 +98,7 @@
#define REQUIRED_MASK13 0
#define REQUIRED_MASK14 0
#define REQUIRED_MASK15 0
-#define REQUIRED_MASK16 (NEED_LA57)
+#define REQUIRED_MASK16 0
#define REQUIRED_MASK17 0
#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
--
2.14.1
--
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next prev parent reply other threads:[~2017-08-21 15:29 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-21 15:28 [PATCHv5 00/19] Boot-time switching between 4- and 5-level paging Kirill A. Shutemov
2017-08-21 15:28 ` [PATCHv5 01/19] mm/sparsemem: Allocate mem_section at runtime for SPARSEMEM_EXTREME Kirill A. Shutemov
2017-08-22 16:28 ` Borislav Petkov
2017-08-22 17:50 ` Kirill A. Shutemov
2017-08-21 15:28 ` [PATCHv5 02/19] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 03/19] x86/kasan: Use the same shadow offset for 4- and 5-level paging Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 04/19] x86/xen: Provide pre-built page tables only for XEN_PV and XEN_PVH Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 05/19] x86/xen: Drop 5-level paging support code from XEN_PV code Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Kirill A. Shutemov
2017-08-27 11:29 ` Cyrill Gorcunov
2017-09-04 13:02 ` Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 07/19] x86/mm: Make virtual memory layout movable for CONFIG_X86_5LEVEL Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 08/19] x86/mm: Make PGDIR_SHIFT and PTRS_PER_P4D variable Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 09/19] x86/mm: Make MAX_PHYSADDR_BITS and MAX_PHYSMEM_BITS dynamic Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 10/19] x86/mm: Make __PHYSICAL_MASK_SHIFT and __VIRTUAL_MASK_SHIFT dynamic Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 11/19] x86/mm: Make STACK_TOP_MAX dynamic Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 12/19] x86/mm: Adjust virtual address space layout in early boot Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 13/19] x86/mm: Make early boot code support boot-time switching of paging modes Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 14/19] x86/mm: Fold p4d page table layer at runtime Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 15/19] x86/mm: Replace compile-time checks for 5-level with runtime-time Kirill A. Shutemov
2017-08-21 15:29 ` Kirill A. Shutemov [this message]
2017-08-21 15:29 ` [PATCHv5 17/19] x86/xen: Allow XEN_PV and XEN_PVH to be enabled with X86_5LEVEL Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 18/19] x86/mm: Redefine some of page table helpers as macros Kirill A. Shutemov
2017-08-21 15:29 ` [PATCHv5 19/19] x86/mm: Offset boot-time paging mode switching cost Kirill A. Shutemov
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