From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D7C1C54E4A for ; Mon, 11 May 2020 12:41:45 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id EB628206D6 for ; Mon, 11 May 2020 12:41:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB628206D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id A05FA900048; Mon, 11 May 2020 08:41:44 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 9DE21900036; Mon, 11 May 2020 08:41:44 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 91A7A900048; Mon, 11 May 2020 08:41:44 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0244.hostedemail.com [216.40.44.244]) by kanga.kvack.org (Postfix) with ESMTP id 774C9900036 for ; Mon, 11 May 2020 08:41:44 -0400 (EDT) Received: from smtpin24.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id 342C540F4 for ; Mon, 11 May 2020 12:41:44 +0000 (UTC) X-FDA: 76804399728.24.mind28_83815c939b52b X-HE-Tag: mind28_83815c939b52b X-Filterd-Recvd-Size: 3708 Received: from huawei.com (szxga05-in.huawei.com [45.249.212.191]) by imf39.hostedemail.com (Postfix) with ESMTP for ; Mon, 11 May 2020 12:41:43 +0000 (UTC) Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D7C869F86BFA885B62CA; Mon, 11 May 2020 20:41:35 +0800 (CST) Received: from [127.0.0.1] (10.173.220.25) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Mon, 11 May 2020 20:41:27 +0800 Subject: Re: [PATCH v2 0/6] arm64: tlb: add support for TTL feature To: , , , , , , , , , , , , , , , , CC: , , , , , , , , References: <20200423135656.2712-1-yezhenyu2@huawei.com> From: Zhenyu Ye Message-ID: <6c59eae9-3a77-ef18-fac4-aa21e97fd1f0@huawei.com> Date: Mon, 11 May 2020 20:41:24 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200423135656.2712-1-yezhenyu2@huawei.com> Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi all, How is this going about this patch series? Does anyone have any suggestions? Thanks, Zhenyu On 2020/4/23 21:56, Zhenyu Ye wrote: > In order to reduce the cost of TLB invalidation, ARMv8.4 provides > the TTL field in TLBI instruction. The TTL field indicates the > level of page table walk holding the leaf entry for the address > being invalidated. This series provide support for this feature. > > When ARMv8.4-TTL is implemented, the operand for TLBIs looks like > below: > > * +----------+-------+----------------------+ > * | ASID | TTL | BADDR | > * +----------+-------+----------------------+ > * |63 48|47 44|43 0| > > > This version updates some codes implementation according to Peter's > suggestion, and adds some commit msg. > > See patches for details, Thanks. > > > -- > ChangeList: > v2: > rebase series on Linux 5.7-rc1 and simplify the code implementation. > > v1: > add support for TTL feature in arm64. > > Marc Zyngier (2): > arm64: Detect the ARMv8.4 TTL feature > arm64: Add level-hinted TLB invalidation helper > > Peter Zijlstra (Intel) (1): > tlb: mmu_gather: add tlb_flush_*_range APIs > > Zhenyu Ye (3): > arm64: Add tlbi_user_level TLB invalidation helper > mm: tlb: Provide flush_*_tlb_range wrappers > arm64: tlb: Set the TTL field in flush_tlb_range > > arch/arm64/include/asm/cpucaps.h | 3 +- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/include/asm/tlb.h | 29 +++++++++++++++- > arch/arm64/include/asm/tlbflush.h | 54 +++++++++++++++++++++++++----- > arch/arm64/kernel/cpufeature.c | 11 +++++++ > include/asm-generic/pgtable.h | 12 +++++-- > include/asm-generic/tlb.h | 55 ++++++++++++++++++++++--------- > mm/pgtable-generic.c | 22 +++++++++++++ > 8 files changed, 160 insertions(+), 27 deletions(-) >