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Wed, 11 Nov 2020 06:33:34 -0800 (PST) MIME-Version: 1.0 References: <20201108064659.GD301837@kernel.org> <7782fb694a6b0c500e8f32ecf895b2bf@agner.ch> <20201110095806.GH301837@kernel.org> <20201110162155.GA4758@kernel.org> <20201111102654.GF4758@kernel.org> <20201111133945.GA12288@alpha.franken.de> In-Reply-To: <20201111133945.GA12288@alpha.franken.de> From: Arnd Bergmann Date: Wed, 11 Nov 2020 15:33:18 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] mm/zsmalloc: include sparsemem.h for MAX_PHYSMEM_BITS To: Thomas Bogendoerfer Cc: Mike Rapoport , Stefan Agner , Minchan Kim , ngupta@vflare.org, Sergey Senozhatsky , Andrew Morton , sjenning@linux.vnet.ibm.com, gregkh , Arnd Bergmann , Linux-MM , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Nov 11, 2020 at 2:39 PM Thomas Bogendoerfer wrote: > On Wed, Nov 11, 2020 at 11:57:02AM +0100, Arnd Bergmann wrote: > > On Wed, Nov 11, 2020 at 11:26 AM Mike Rapoport wrote: > > > > > > On Wed, Nov 11, 2020 at 10:33:29AM +0100, Arnd Bergmann wrote: > > > > On Tue, Nov 10, 2020 at 5:21 PM Mike Rapoport wrote: > > > > > On Tue, Nov 10, 2020 at 12:21:11PM +0100, Arnd Bergmann wrote: > > > > > > > > > > > > To be on the safe side, we could provoke a compile-time error > > > > > > when CONFIG_PHYS_ADDR_T_64BIT is set on a 32-bit > > > > > > architecture, but MAX_POSSIBLE_PHYSMEM_BITS is not set. > > > > > > > > > > Maybe compile time warning and a runtime error in zs_init() if 32 bit > > > > > machine has memory above 4G? > > > > > > > > If the fix is as easy as adding a single line in a header, I think a > > > > compile-time > > > > error makes it easier, no need to wait for someone to boot a broken > > > > system before fixing it. > > > > > > Not sure it would be as easy as adding a single line in a header for > > > MIPS with it's diversity. > > > > I looked up the architecture, and found: > > > > - The pre-MIPS32r1 cores only support 32-bit addressing > > - octeon selects PHYS_ADDR_T_64BIT but no longer > > supports 32-bit kernels > > - Alchemy and netlogic (XLR, XLP) have 36-bit addressing > > - CONFIG_XPA implies 40-bit addressing > > MIPS32r5 might have up to 60-bit addressing according to the MIPS32 PRA > docuemnt (MD00090). But there is probably no chip, which implements it > so for now 40-bit addressing is correct. > > > > > We should run it by the MIPS maintainers, but I think this patch > > is sufficient: > > Do you want me to run it through mips tree or do you need an > Acked-By from me ? I'll follow up with a proper submission for MIPS and the other architectures, please apply that one. Arnd