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From: Maxime Ripard <maxime@cerno.tech>
To: Eric Biggers <ebiggers@kernel.org>
Cc: linux-mmc@vger.kernel.org, Ulf Hansson <ulf.hansson@linaro.org>
Subject: Help with eMMC inline encryption
Date: Wed, 17 Mar 2021 18:15:54 +0100	[thread overview]
Message-ID: <20210317171554.a4vgihqfjq2xa5cb@gilmour> (raw)

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Hi Eric,

I've followed your work to integrate fscrypt for an eMMC, and now that
it's been merged started to write the support for the Allwinner H6 [1]
that has an encryption / decryption engine (EMCE, page 332) for the eMMC
controller (page 495).

I have some code that does most of the work to enable it and I'm at a
point where I can run xfstests (so the accesses seem to go through the
crypto engine, and they decrypt something), but the content of the files
are off compared to the software implementation.

My first guess would be to check how the key is setup in the hardware,
but it's where I'm not really sure what's going on. It looks from the
cqhci driver that the AES-XTS key has twice the size, and it's written
in two steps for some reason? [2]

Since the AES-XTS key size allegedly supported by the driver is 256 bits
but the key size is 64 bytes, the comment makes sense, but I'm not
really sure what is happening and what I'm supposed to be doing with
that key.

Thanks!
Maxime

1: http://files.pine64.org/doc/datasheet/pine-h64/Allwinner_H6%20V200_User_Manual_V1.1.pdf
2: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/cqhci-crypto.c#n92

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             reply	other threads:[~2021-03-17 17:17 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-17 17:15 Maxime Ripard [this message]
2021-03-17 18:33 ` Help with eMMC inline encryption Eric Biggers
2021-03-22 15:53   ` Maxime Ripard
2021-03-22 17:02     ` Eric Biggers
2021-03-23 10:53       ` Maxime Ripard

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