From: Michael Walle <michael@walle.cc>
To: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Cc: greg.malysa@timesys.com,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Pratyush Yadav <pratyush@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/3] mtd: spi-nor: Add additional octal-mode flags to be checked during SFDP
Date: Thu, 01 Dec 2022 23:08:42 +0100 [thread overview]
Message-ID: <0537b888aa4e6b7ce4194e8242a231fd@walle.cc> (raw)
In-Reply-To: <20221201212750.267721-3-nathan.morrison@timesys.com>
[In general, please post new versions after a reasonable
amount of time for reviews. Like a day or so.]
Am 2022-12-01 22:27, schrieb Nathan Barrett-Morrison:
> This adds some support for searching a chips SFDP table for:
>
> read commands: 1S-8S-8S
> program commands: 1S-1S-8S, 1S-8S-8S
>
> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> ---
> drivers/mtd/spi-nor/core.c | 8 ++++++++
> drivers/mtd/spi-nor/core.h | 5 +++--
> drivers/mtd/spi-nor/sfdp.c | 8 ++++++++
> 3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index bee8fc4c9f07..2f882608abc6 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2359,6 +2359,13 @@ static void spi_nor_no_sfdp_init_params(struct
> spi_nor *nor)
> SNOR_PROTO_1_1_8);
> }
>
> + if (no_sfdp_flags & SPI_NOR_OCTAL_READ_1_8_8) {
> + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_8_8],
> + 0, 16, SPINOR_OP_READ_1_8_8,
> + SNOR_PROTO_1_8_8);
> + }
This should only be done for flashes which doesn't support
SFDP at all (see the comment for spi_nor_no_sfdp_init_params()).
Yours supports SFDP, has the correct flags in the
4BAIT table but doesn't have the 17th DWORD in the BFPT. I'm not
sure if this is correct or if it's a mistake in the SFDP of this
flash device.
If it's correct, we would need to somehow call
spi_nor_set_read_settings() in sfdp.c; but we don't know the
mode or wait clocks. If it's a mistake in the SFDP, we'd need
to add a fixup for this particular flash which sets the read
settings. I'd go with the second because we just haven't enough
information.
-michael
> +
> if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
> params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
> spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
> @@ -2514,6 +2521,7 @@ static void
> spi_nor_init_params_deprecated(struct spi_nor *nor)
> if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ |
> SPI_NOR_OCTAL_READ |
> + SPI_NOR_OCTAL_READ_1_8_8 |
> SPI_NOR_OCTAL_DTR_READ))
> spi_nor_sfdp_init_params_deprecated(nor);
> }
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 85b0cf254e97..7bc1cde049b7 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -514,8 +514,9 @@ struct flash_info {
> #define SPI_NOR_DUAL_READ BIT(3)
> #define SPI_NOR_QUAD_READ BIT(4)
> #define SPI_NOR_OCTAL_READ BIT(5)
> -#define SPI_NOR_OCTAL_DTR_READ BIT(6)
> -#define SPI_NOR_OCTAL_DTR_PP BIT(7)
> +#define SPI_NOR_OCTAL_READ_1_8_8 BIT(6)
> +#define SPI_NOR_OCTAL_DTR_READ BIT(7)
> +#define SPI_NOR_OCTAL_DTR_PP BIT(8)
>
> u8 fixup_flags;
> #define SPI_NOR_4B_OPCODES BIT(0)
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index e4e87815ba94..e1b7547bf81e 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -1089,6 +1089,14 @@ static int spi_nor_parse_4bait(struct spi_nor
> *nor,
> spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
> SPINOR_OP_PP_1_4_4_4B,
> SNOR_PROTO_1_4_4);
> + if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_8)
> + spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_8],
> + SPINOR_OP_PP_1_1_8_4B,
> + SNOR_PROTO_1_1_8);
> + if (pp_hwcaps & SNOR_HWCAPS_PP_1_8_8)
> + spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_8_8],
> + SPINOR_OP_PP_1_8_8_4B,
> + SNOR_PROTO_1_8_8);
>
> for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
> if (erase_mask & BIT(i))
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next prev parent reply other threads:[~2022-12-01 22:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 21:27 [PATCH v3 0/3] mtd: spi-nor: Extend SFDP to support additional octal modes as per latest JEDEC standard Nathan Barrett-Morrison
2022-12-01 21:27 ` [PATCH v3 1/3] mtd: spi-nor: Extend SFDP 4byte address instruction lookup table with new octal modes as per JEDEC JESD216F Nathan Barrett-Morrison
2022-12-01 21:27 ` [PATCH v3 2/3] mtd: spi-nor: Add additional octal-mode flags to be checked during SFDP Nathan Barrett-Morrison
2022-12-01 22:08 ` Michael Walle [this message]
2022-12-01 21:27 ` [PATCH v3 3/3] mtd: spi-nor: Add support for IS25LX256 operating in 1S-8S-8S octal read mode Nathan Barrett-Morrison
2022-12-01 22:12 ` Michael Walle
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