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From: <Tudor.Ambarus@microchip.com>
To: <roman@advem.lv>, <linux-mtd@lists.infradead.org>
Cc: marek.vasut@gmail.com
Subject: Re: [PATCH 1/2] mtd: spi-nor: fix GigaDevice quad_enable
Date: Sun, 28 Jul 2019 05:48:30 +0000	[thread overview]
Message-ID: <11718527-0145-a99d-83fe-19885c9609f0@microchip.com> (raw)
In-Reply-To: <20190726210830.1932-1-roman@advem.lv>

Hi, Roman,

On 07/27/2019 12:08 AM, Roman Yeryomin wrote:
> External E-Mail
> 
> 
> According to datasheets all GD devices are capable of quad mode, which

Does any of these flashes implement the Basic Flash Parameter Table? Can't we
determine the QE Requirements by parsing BFPT?

> is enabled via Status Register-2, bit 1 (S9). This corresponds to
> Spansion SR/CR operations. Unfortunately only gd25q256 datasheet is
> clear about Quad Enable Requirements (QER), others have no such
> information in datasheets.
> So define quad_enable for all GD devices to be sure.

Which flash did you test?

Cheers,
ta

> Also gd25q256 is an exception. There are two versions: C and D.
> First one uses S6 bit (like described in e27072851bf7d) but the latter
> uses S9 bit like others. To add support for D this should be handled
> differently, so, to retain compatibility, leave gd25q256 quad_enable
> callback intact.
> 
> Signed-off-by: Roman Yeryomin <roman@advem.lv>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
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  reply	other threads:[~2019-07-28  5:49 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-26 21:08 [PATCH 1/2] mtd: spi-nor: fix GigaDevice quad_enable Roman Yeryomin
2019-07-28  5:48 ` Tudor.Ambarus [this message]
2019-07-28  6:21   ` Tudor.Ambarus
2019-08-07 20:10     ` Roman Yeryomin
2019-07-28  8:47 ` Sergei Shtylyov

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