Prevent Nand page writes on Power failure

[Sascha Hauer <s.hauer@pengutronix.de>]

Hi All,

I have hardware here for which the normal way to turn off is just to cut
the power. When the powercut happens during a NAND page write then we
get more or less completely written pages during next boot. Very rarely
it seems to happen that such a half written page with only very few
flipped bits is erroneously detected as empty and written again which
then results in ECC errors when reading the data.

The Nand in question is a Micron MT29F4G08ABADAH4 and in TN2917 Micron
clearly states:

| Power loss during NAND array operations (especially Program/Erase) is a
| violation of the NAND voltage specifications, which is not supported and
| should be avoided

Micron suggests to make the capacitors on the Nand chips supply input
big enough that every started operation will be finished before the
power goes down. Now we don't have that situation here, what I have
though is a power good status GPIO, so my job is to wire that up to the
Nand write operations.

Now my question is how could that be done? I assume for some people a
power good failure means that we should write all important data away,
rather than preventing any Nand access. Given it's a policy decision I
assume user space should be involved, right?  An option might be to
introcude some sysfs entry to switch mtd devices to readonly mode. Would
that be fine? Other suggestions?

Sascha

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