From: Jungseung Lee <js07.lee@samsung.com>
To: Marek Vasut <marek.vasut@gmail.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Boris Brezillon <bbrezillon@kernel.org>,
Richard Weinberger <richard@nod.at>,
u.kleine-koenig@pengutronix.de, linux-mtd@lists.infradead.org,
js07.lee@gmail.com, js07.lee@samsung.com
Subject: [PATCH v4 5/5] mtd: spi-nor: support lock/unlock for a few Micron chips
Date: Sat, 13 Jul 2019 23:59:38 +0900 [thread overview]
Message-ID: <20190713145938.19203-5-js07.lee@samsung.com> (raw)
In-Reply-To: <20190713145938.19203-1-js07.lee@samsung.com>
Some Micron models are known to have lock/unlock support,
and that also support 4bit block protection bit (bp0-3).
This patch support lock/unlock feature on the flash.
Tested on w25q512ax3. The Other is modified following the datasheet.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0fee22068d94..f7d6aad4281e 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2056,8 +2056,16 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
- { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ {
+ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3)
+ },
+ {
+ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3)
+ },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
--
2.17.1
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prev parent reply other threads:[~2019-08-01 10:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190801102545epcas1p4e40553b44ec941ffa82c0f9bc6943c2c@epcas1p4.samsung.com>
2019-07-13 14:59 ` [PATCH v4 1/5] mtd: spi-nor: rename SR_TB to indicate the bit used Jungseung Lee
[not found] ` <CGME20190801102545epcas1p30a36729bcb5b727177a9bf395f09cc77@epcas1p3.samsung.com>
2019-07-13 14:59 ` [PATCH v4 2/5] mtd: spi-nor: Fix wrong TB selection on winbond/gigadevice flashes Jungseung Lee
[not found] ` <CGME20190801102545epcas1p2966140195425fef491d607e3c183f22a@epcas1p2.samsung.com>
2019-07-13 14:59 ` [PATCH v4 3/5] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
[not found] ` <CGME20190801102545epcas1p2ea4a29c514a6c54813f379cc7b7110dd@epcas1p2.samsung.com>
2019-07-13 14:59 ` [PATCH v4 4/5] mtd: spi-nor: add 4bit block protection support Jungseung Lee
[not found] ` <CGME20190801102545epcas1p46bf16362a9a2dbf39e2caff85813807c@epcas1p4.samsung.com>
2019-07-13 14:59 ` Jungseung Lee [this message]
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