From: <Tudor.Ambarus@microchip.com>
To: <vigneshr@ti.com>, <boris.brezillon@collabora.com>,
<marek.vasut@gmail.com>, <miquel.raynal@bootlin.com>,
<richard@nod.at>, <linux-mtd@lists.infradead.org>
Cc: linux-aspeed@lists.ozlabs.org, Tudor.Ambarus@microchip.com,
andrew@aj.id.au, linux-kernel@vger.kernel.org, vz@mleia.com,
linux-mediatek@lists.infradead.org, joel@jms.id.au,
matthias.bgg@gmail.com, computersforpeace@gmail.com,
dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable()
Date: Tue, 17 Sep 2019 15:55:45 +0000 [thread overview]
Message-ID: <20190917155426.7432-21-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20190917155426.7432-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename the method to spi_nor_sr2_bit7_quad_enable(). Do the
read back test on all the eight bits of the Status Register,
not just the QE one.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8648666fb9bd..a9cdb6dbc25c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1994,7 +1994,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
}
/**
- * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
+ * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
* @nor: pointer to a 'struct spi_nor'
*
* Set the Quad Enable (QE) bit in the Status Register 2.
@@ -2005,10 +2005,11 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
*
* Return: 0 on success, -errno otherwise.
*/
-static int sr2_bit7_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
{
u8 *sr2 = nor->bouncebuf;
int ret;
+ u8 sr2_written;
/* Check current Quad Enable bit value. */
ret = spi_nor_read_sr2(nor, sr2);
@@ -2025,13 +2026,15 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
+ sr2_written = *sr2;
+
/* Read back and check it. */
ret = spi_nor_read_sr2(nor, sr2);
if (ret)
return ret;
- if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
- dev_err(nor->dev, "SR2 Quad bit not set\n");
+ if (*sr2 != sr2_written) {
+ dev_err(nor->dev, "Read back test failed\n");
return -EIO;
}
@@ -3605,7 +3608,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_SR2_BIT7:
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- flash->quad_enable = sr2_bit7_quad_enable;
+ flash->quad_enable = spi_nor_sr2_bit7_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT1:
--
2.9.5
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next prev parent reply other threads:[~2019-09-17 16:07 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
2019-09-19 17:34 ` Vignesh Raghavendra
2019-09-20 4:42 ` Tudor.Ambarus
2019-09-17 15:55 ` Tudor.Ambarus [this message]
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
2019-09-19 16:07 ` Tudor.Ambarus
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