From: Mark Brown <broonie@kernel.org>
To: John Garry <john.garry@huawei.com>
Cc: tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org,
linuxarm@huawei.com, linux-spi@vger.kernel.org,
marek.vasut@gmail.com, linux-mtd@lists.infradead.org,
xuejiancheng@hisilicon.com, fengsheng5@huawei.com
Subject: Re: [PATCH 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Mon, 4 Nov 2019 19:24:06 +0000 [thread overview]
Message-ID: <20191104192406.GH5238@sirena.co.uk> (raw)
In-Reply-To: <1572886297-45400-3-git-send-email-john.garry@huawei.com>
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On Tue, Nov 05, 2019 at 12:51:36AM +0800, John Garry wrote:
> Only ACPI firmware is supported.
There's no ACPI dependency though? If the driver only works with ACPI
I'd expect to see one with an || COMPILE_TEST like the architecture
dependency.
> @@ -0,0 +1,287 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
> + *
Please make the entire comment a C++ one for neatness.
> + * Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
> + * Author: John Garry <john.garry@huawei.com>
> + */
> +//#define DEBUG 1
Please remove this.
> +#define GLOBAL_CFG (0x100)
> +
> +#define BUS_CFG1 (0x200)
> +#define BUS_CFG2 (0x204)
> +#define BUS_FLASH_SIZE (0x210)
> +
> +#define VERSION (0x1f8)
These could use some namespacing, especially the last one - it seems
quite likely there'll be some collisions at some point.
> +#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
> +#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
Plus if we've got these long prefixes here it'd be good to be
consistent.
> + if (IS_ALIGNED((uintptr_t)to, 4)) {
> + int words = len / 4;
> +
> + __ioread32_copy(to, host->regbase + CMD_DATABUF(0), words);
> +
> + len -= words * 4;
> + if (len) {
> + u32 val;
> +
> + val = __raw_readl(host->regbase + CMD_DATABUF(words));
> +
> + to += words * 4;
> + for (i = 0; i < len; i++, val >>= 8, to++)
> + *to = (u8)val;
> + }
> + } else {
> + for (i = 0; i < DIV_ROUND_UP(len, 4); i++) {
> + u32 val = __raw_readl(host->regbase + CMD_DATABUF(i));
> + int j;
The more usual pattern for these would be to do some unaligned accesses
for the start/end of the buffer to get to alignment and then transfer
the rest as aligned data.
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next prev parent reply other threads:[~2019-11-04 19:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-04 16:51 [PATCH 0/3] HiSilicon v3xx SFC driver John Garry
2019-11-04 16:51 ` [PATCH 1/3] mtd: spi-nor: hisi-sfc: Try to provide some clarity on which SFC we are John Garry
2019-11-04 16:51 ` [PATCH 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver John Garry
2019-11-04 19:24 ` Mark Brown [this message]
2019-11-05 10:58 ` John Garry
2019-11-05 11:05 ` Mark Brown
2019-11-05 16:04 ` John Garry
2019-11-04 16:51 ` [PATCH 3/3] MAINTAINERS: Add a maintainer for the HiSilicon v3xx SFC driver John Garry
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